Aadi Desai
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8e47dd4696
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Add brief project description
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2022-09-16 11:39:12 +01:00 |
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Aadi Desai
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0ad87f0c97
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Optimised sumVector
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2022-02-17 19:03:56 +00:00 |
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Aadi Desai
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00405c820c
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Task 5
Update QSYS, add PLL block, update main C file to Task 5 end
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2022-02-02 15:56:35 +00:00 |
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Aadi Desai
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8ed2b5bc0e
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Task 1 & 2
Add source files and update to completed state at end of Task 2
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2022-01-30 17:18:39 +00:00 |
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Aadi Desai
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94e215043a
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Add specific entries to .gitignore
For Verilog and C source files within project
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2022-01-30 17:17:51 +00:00 |
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Aadi Desai
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dc28e5c175
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Initial Commit
Include Coursework PDF and basic test script for checking answer in Python
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2022-01-25 16:48:03 +00:00 |
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