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Add specific entries to .gitignore

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For Verilog and C source files within project
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Aadi Desai 2022-01-30 17:17:51 +00:00
parent dc28e5c175
commit 94e215043a
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@ -1,6 +1,11 @@
**
!system_template_de1_soc/
!*.v
!*.qsys
!system_template_de1_soc/software/
!system_template_de1_soc/software/*
system_template_de1_soc/software/*_bsp
!system_template_de1_soc/software/*/*.c
!DSD_coursework_DE1-SoC.pdf
!README.md
!Python/