supleed2/ELEC60011-DSD-CW
1
0
Fork 0
mirror of https://github.com/supleed2/ELEC60011-DSD-CW.git synced 2024-12-22 13:45:48 +00:00
Code Issues Packages Projects Releases Wiki Activity
Coursework for ELEC60011: Digital System Design - a Quartus project containing a NIOS II soft-core and custom instruction hardware accelerators for the target function
2 commits 1 branch 0 tags 2.1 MiB
Verilog 63.5%
VHDL 18.1%
Tcl 16.9%
C 1.2%
Python 0.3%
Go to file
Aadi Desai 94e215043a
Add specific entries to .gitignore 
For Verilog and C source files within project
2022-01-30 17:17:51 +00:00
Python Initial Commit 2022-01-25 16:48:03 +00:00
.gitignore Add specific entries to .gitignore 2022-01-30 17:17:51 +00:00
DSD_coursework_DE1-SoC.pdf Initial Commit 2022-01-25 16:48:03 +00:00
README.md Initial Commit 2022-01-25 16:48:03 +00:00

README.md

ELEC60011: Digital System Design - Coursework