ELEC60011-DSD-CW/.gitignore
Aadi Desai 94e215043a
Add specific entries to .gitignore
For Verilog and C source files within project
2022-01-30 17:17:51 +00:00

12 lines
245 B
Plaintext

**
!system_template_de1_soc/
!*.v
!*.qsys
!system_template_de1_soc/software/
!system_template_de1_soc/software/*
system_template_de1_soc/software/*_bsp
!system_template_de1_soc/software/*/*.c
!DSD_coursework_DE1-SoC.pdf
!README.md
!Python/
!*.py