From 94e215043a194f4ee8e773b19920f117ea707cfc Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Sun, 30 Jan 2022 17:17:51 +0000
Subject: [PATCH] Add specific entries to .gitignore

For Verilog and C source files within project
---
 .gitignore | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/.gitignore b/.gitignore
index b475684..c5294c7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,11 @@
 **
+!system_template_de1_soc/
 !*.v
 !*.qsys
+!system_template_de1_soc/software/
+!system_template_de1_soc/software/*
+system_template_de1_soc/software/*_bsp
+!system_template_de1_soc/software/*/*.c
 !DSD_coursework_DE1-SoC.pdf
 !README.md
 !Python/