supleed2/ELEC60011-DSD-CW
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Coursework for ELEC60011: Digital System Design - a Quartus project containing a NIOS II soft-core and custom instruction hardware accelerators for the target function
4 commits 1 branch 0 tags 2.1 MiB
Verilog 63.5%
VHDL 18.1%
Tcl 16.9%
C 1.2%
Python 0.3%
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Aadi Desai 00405c820c
Task 5 
Update QSYS, add PLL block, update main C file to Task 5 end
2022-02-02 15:56:35 +00:00
Python Task 1 & 2 2022-01-30 17:18:39 +00:00
system_template_de1_soc Task 5 2022-02-02 15:56:35 +00:00
.gitignore Add specific entries to .gitignore 2022-01-30 17:17:51 +00:00
DSD_coursework_DE1-SoC.pdf Initial Commit 2022-01-25 16:48:03 +00:00
README.md Initial Commit 2022-01-25 16:48:03 +00:00

README.md

ELEC60011: Digital System Design - Coursework