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Coursework for ELEC60011: Digital System Design - a Quartus project containing a NIOS II soft-core and custom instruction hardware accelerators for the target function
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Verilog 63.5%
VHDL 18.1%
Tcl 16.9%
C 1.2%
Python 0.3%
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Aadi Desai dc28e5c175
Initial Commit 
Include Coursework PDF and basic test script for checking answer in Python
2022-01-25 16:48:03 +00:00
Python Initial Commit 2022-01-25 16:48:03 +00:00
.gitignore Initial Commit 2022-01-25 16:48:03 +00:00
DSD_coursework_DE1-SoC.pdf Initial Commit 2022-01-25 16:48:03 +00:00
README.md Initial Commit 2022-01-25 16:48:03 +00:00

README.md

ELEC60011: Digital System Design - Coursework