Aadi Desai
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ad394c7d7d
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Adding missing opcodes to CtrlMemRead
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2020-12-17 09:02:58 -08:00 |
|
Aadi Desai
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cb29efd034
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Merge branch 'main' into bus_wrapper
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2020-12-17 16:46:01 +00:00 |
|
Aadi Desai
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2be1978a36
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Add initial value to npc, add JR to CtrlMemRead
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2020-12-17 08:43:58 -08:00 |
|
Aadi Desai
|
1ae5d78b4d
|
Added dummy clk_enable to harvard instance, added clock kickstart after reset
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2020-12-17 07:58:33 -08:00 |
|
Aadi Desai
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74681e8890
|
Stall bus memory when reset is high
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2020-12-17 07:34:32 -08:00 |
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jl7719
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cfebb403ba
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Delete from source files and the testbench
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2020-12-17 15:02:59 +00:00 |
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jl7719
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2d9cca262d
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Fix display appearing at the end of log file
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2020-12-17 14:51:08 +00:00 |
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Aadi Desai
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e89087c127
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Bus Memory typo in bus script
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2020-12-17 06:34:42 -08:00 |
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theexecutor13
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6c400f3567
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uploading log.txt weirdness testcase
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2020-12-17 14:31:33 +00:00 |
|
Aadi Desai
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2eccc5148e
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Move bus memory from rtl to testbench folder
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2020-12-17 13:58:07 +00:00 |
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Aadi Desai
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af29f22651
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Merge branch 'main' into bus_wrapper
Changes to be duplicated for bus version
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2020-12-17 13:54:26 +00:00 |
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theexecutor13
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0bdbb63f49
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Update reference.txt
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2020-12-17 21:37:17 +08:00 |
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theexecutor13
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7fcc2486cb
|
cleanup
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2020-12-17 13:37:00 +00:00 |
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theexecutor13
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ab13c84ef5
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testing branch delay slot
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2020-12-17 12:03:30 +00:00 |
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theexecutor13
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4ab4809a8a
|
restructuring
|
2020-12-17 11:47:13 +00:00 |
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theexecutor13
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15dfce09c9
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Update reference.txt
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2020-12-17 19:44:23 +08:00 |
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jl7719
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6e626c5931
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Change location of the memory module from rtl to testbench
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2020-12-17 10:32:52 +00:00 |
|
Aadi Desai
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33bb4c7538
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Constant selects not working in always_ff in current iverilog
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2020-12-16 14:21:26 -08:00 |
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Aadi Desai
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5e62dd82d8
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Add bus vcd to gitignore, fix missing case in bus
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2020-12-16 14:08:28 -08:00 |
|
Aadi Desai
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d17060b0a1
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Add missing end to if statement
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2020-12-16 13:54:01 -08:00 |
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Aadi Desai
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da0c9aba01
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Fix {} for bit duplication, remove module name from endmodule
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2020-12-16 13:38:09 -08:00 |
|
Aadi Desai
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744aee097f
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Modify bus tb to compile bus version instead
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2020-12-16 20:15:08 +00:00 |
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Aadi Desai
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4534ca6760
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Add custom test script for bus tb
Bus specific testcases have been uncommented (sb, sh)
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2020-12-16 20:09:08 +00:00 |
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Aadi Desai
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2f9b08a363
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Updated bus tb to match harvard tb
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2020-12-16 20:05:00 +00:00 |
|
Aadi Desai
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a31ed073e1
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Merge branch 'main' into bus_wrapper
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2020-12-16 19:57:28 +00:00 |
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Aadi Desai
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20880f6ab2
|
Complete avalon bus memory
Read and write logic (including partial writes using byte enables) complete. Address is always word aligned, as handled within bus wrapper.
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2020-12-16 19:20:48 +00:00 |
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jl7719
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697b6e0a9e
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Update some testcases for branch delay slots
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2020-12-16 17:13:39 +00:00 |
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jl7719
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ec275418b7
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Update harvard testbench regarding resets
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2020-12-16 16:59:28 +00:00 |
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jl7719
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1f7027f771
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Update harvard test script to match spec
main branch ignore bus implementation
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2020-12-16 16:46:27 +00:00 |
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Aadi Desai
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f5fea77ea7
|
General structure of bus memory
Read and Write logic to be added
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2020-12-16 08:42:26 -08:00 |
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jl7719
|
4be3149300
|
Update test_mips_cpu_bus.sh
Needs checking for source file for bus version
|
2020-12-16 15:58:03 +00:00 |
|
Aadi Desai
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d8c918c9b4
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Merge branch 'main' into bus_wrapper
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2020-12-16 15:41:56 +00:00 |
|
Aadi Desai
|
252f630162
|
Cleanup
|
2020-12-16 15:40:21 +00:00 |
|
Aadi Desai
|
1a413d9686
|
Merge branch 'main' into jl7719
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2020-12-16 15:40:07 +00:00 |
|
jl7719
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ebe33ce56a
|
Passes all tests
|
2020-12-16 15:29:04 +00:00 |
|
Jeevaha Coelho
|
7185f7e7e6
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Fixed BGEZAL
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2020-12-16 07:00:46 -08:00 |
|
Aadi Desai
|
67682ecfde
|
Create basic bus memory block
I/O, parameters and initial setup block included
|
2020-12-16 14:07:43 +00:00 |
|
Jeevaha Coelho
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2673e23137
|
FIxed PC!
|
2020-12-16 05:21:57 -08:00 |
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jl7719
|
ad68ab0974
|
Debugging and debugging
PC, Jump instr, branches
|
2020-12-16 12:29:22 +00:00 |
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jl7719
|
0891f7e653
|
Debug mult/div to work
it works now
|
2020-12-16 08:38:46 +00:00 |
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jl7719
|
4ff160db1a
|
Fix syntax errors from mult/div
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2020-12-16 05:04:45 +00:00 |
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yhp19
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07d32e9baf
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fixed input file plz document ur change in reference.txt
|
2020-12-16 12:27:48 +08:00 |
|
Jeevaha Coelho
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864c8b6964
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Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into jl7719
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2020-12-15 13:48:50 -08:00 |
|
Jeevaha Coelho
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90917f7566
|
Updated PC, Harv, ALU, to work w/ MULT(U), DIV(U)
|
2020-12-15 13:48:28 -08:00 |
|
yhp19
|
b54092cd57
|
reference txt
|
2020-12-16 01:00:03 +08:00 |
|
yhp19
|
cc5d2bbeab
|
changes to input files
|
2020-12-16 00:57:46 +08:00 |
|
theexecutor13
|
6e600966db
|
Update reference.txt
|
2020-12-16 00:06:33 +08:00 |
|
jl7719
|
85efff275a
|
Fix program counter taking two cycles for each instr
|
2020-12-15 15:53:30 +00:00 |
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jl7719
|
01a3b9a973
|
Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into jl7719
merge
|
2020-12-15 15:20:43 +00:00 |
|
jl7719
|
fc5c8a17f5
|
Fix signed error in alu block
|
2020-12-15 15:19:51 +00:00 |
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