supleed2/ELEC50010-IAC-CW
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91 commits

Author SHA1 Message Date
Aadi Desai 49b7fdbe07
Update Harvard for new regfile input 2020-12-19 10:27:17 +00:00
Aadi Desai a598321539
Use base+offset[1:0] for partial loads instead of base[1:0] 2020-12-19 10:22:44 +00:00
Aadi Desai e513096ed8 Add missing opcodes to CtrlMemRead = 0 2020-12-17 09:43:47 -08:00
Aadi Desai 6687cb8e17 Bring read signal low with clk during read cycle 2020-12-17 09:43:04 -08:00
Aadi Desai ad394c7d7d Adding missing opcodes to CtrlMemRead 2020-12-17 09:02:58 -08:00
Aadi Desai cb29efd034 Merge branch 'main' into bus_wrapper 2020-12-17 16:46:01 +00:00
Aadi Desai 2be1978a36 Add initial value to npc, add JR to CtrlMemRead 2020-12-17 08:43:58 -08:00
Aadi Desai 1ae5d78b4d Added dummy clk_enable to harvard instance, added clock kickstart after reset 2020-12-17 07:58:33 -08:00
jl7719 cfebb403ba Delete from source files and the testbench 2020-12-17 15:02:59 +00:00
jl7719 2d9cca262d Fix display appearing at the end of log file 2020-12-17 14:51:08 +00:00
Aadi Desai 2eccc5148e Move bus memory from rtl to testbench folder 2020-12-17 13:58:07 +00:00
Aadi Desai af29f22651 Merge branch 'main' into bus_wrapper 
Changes to be duplicated for bus version
 2020-12-17 13:54:26 +00:00
jl7719 6e626c5931 Change location of the memory module from rtl to testbench 2020-12-17 10:32:52 +00:00
Aadi Desai 33bb4c7538 Constant selects not working in always_ff in current iverilog 2020-12-16 14:21:26 -08:00
Aadi Desai 5e62dd82d8 Add bus vcd to gitignore, fix missing case in bus 2020-12-16 14:08:28 -08:00
Aadi Desai d17060b0a1 Add missing end to if statement 2020-12-16 13:54:01 -08:00
Aadi Desai da0c9aba01 Fix {} for bit duplication, remove module name from endmodule 2020-12-16 13:38:09 -08:00
Aadi Desai 20880f6ab2 Complete avalon bus memory 
Read and write logic (including partial writes using byte enables) complete. Address is always word aligned, as handled within bus wrapper.
 2020-12-16 19:20:48 +00:00
jl7719 1f7027f771 Update harvard test script to match spec 
main branch ignore bus implementation
 2020-12-16 16:46:27 +00:00
Aadi Desai f5fea77ea7 General structure of bus memory 
Read and Write logic to be added
 2020-12-16 08:42:26 -08:00
Aadi Desai d8c918c9b4 Merge branch 'main' into bus_wrapper 2020-12-16 15:41:56 +00:00
jl7719 ebe33ce56a Passes all tests 2020-12-16 15:29:04 +00:00
Jeevaha Coelho 7185f7e7e6 Fixed BGEZAL 2020-12-16 07:00:46 -08:00
Aadi Desai 67682ecfde Create basic bus memory block 
I/O, parameters and initial setup block included
 2020-12-16 14:07:43 +00:00
Jeevaha Coelho 2673e23137 FIxed PC! 2020-12-16 05:21:57 -08:00
jl7719 ad68ab0974 Debugging and debugging 
PC, Jump instr, branches
 2020-12-16 12:29:22 +00:00
jl7719 0891f7e653 Debug mult/div to work 
it works now
 2020-12-16 08:38:46 +00:00
jl7719 4ff160db1a Fix syntax errors from mult/div 2020-12-16 05:04:45 +00:00
Jeevaha Coelho 90917f7566 Updated PC, Harv, ALU, to work w/ MULT(U), DIV(U) 2020-12-15 13:48:28 -08:00
jl7719 85efff275a Fix program counter taking two cycles for each instr 2020-12-15 15:53:30 +00:00
jl7719 fc5c8a17f5 Fix signed error in alu block 2020-12-15 15:19:51 +00:00
Jeevaha Coelho 85ba783a69 Fixed signing error in alu and added excel file 2020-12-15 05:21:37 -08:00
Jeevaha Coelho 5df8a72ca1 fixed naming convention errors in pc and harvard 2020-12-15 03:16:01 -08:00
jl7719 51dbe68ea8 Fix running on different environment issue 
Now completely shifted to Ubuntu 18.04 setup should work for everyone
 2020-12-14 17:38:39 +00:00
jl7719 7150487472 Rename initialisation files 2020-12-13 14:54:53 +09:00
jl7719 943745a1e0 Tested all that can be tested for now 
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
 2020-12-13 14:40:16 +09:00
Aadi Desai 1123477690 Mask address during partial writes 2020-12-13 00:15:15 +00:00
Aadi Desai 50b9dba651 Added partial writes 
SH and SB were not accounted for in previous version, partial reads are handled within regfile
 2020-12-12 16:49:02 +00:00
jl7719 c31344c55f More testcases, testing, debugging 2020-12-13 01:25:36 +09:00
jl7719 14ad7fa0ce Update program counter 
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
 2020-12-12 15:59:14 +09:00
Aadi Desai af7645b5b0 Completed wrapper, to be tested 2020-12-11 19:45:00 +00:00
Aadi Desai 714b74ec83 Update mips_cpu_bus.v 
Added fetch/execute states. All instructions not using data memory should function
 2020-12-11 19:13:11 +00:00
Aadi Desai 7997076be7 Basic Wrapper, Logic to be added 2020-12-11 10:56:34 +00:00
jl7719 3594365a25 Create branch jl7719 
Can test for normal pc incrementing instr
 2020-12-11 19:45:13 +09:00
jl7719 7ffd8fb400 Add testcases and ref outputs for addiu, and, andi 2020-12-11 15:17:43 +09:00
jl7719 04b1ed4fed Update control and memory 
Fixed some errors when testing
 2020-12-10 22:27:08 +09:00
jl7719 84adff2ed1 Update memory 
No longer need the massive memory
 2020-12-10 19:14:16 +09:00
jc4419 3a2fde81b2 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-09 16:27:20 +04:00
jc4419 4b8a56ee2f Fixed if logic for control 2020-12-09 16:24:21 +04:00
jl7719 c5aed43ab4 Update to test each instruction with a small memory 2020-12-09 16:47:58 +09:00