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Author SHA1 Message Date
Aadi Desai 20880f6ab2 Complete avalon bus memory 
Read and write logic (including partial writes using byte enables) complete. Address is always word aligned, as handled within bus wrapper.
 2020-12-16 19:20:48 +00:00
Aadi Desai f5fea77ea7 General structure of bus memory 
Read and Write logic to be added
 2020-12-16 08:42:26 -08:00
jl7719 4be3149300 Update test_mips_cpu_bus.sh 
Needs checking for source file for bus version
 2020-12-16 15:58:03 +00:00
Aadi Desai d8c918c9b4 Merge branch 'main' into bus_wrapper 2020-12-16 15:41:56 +00:00
Aadi Desai 252f630162 Cleanup 2020-12-16 15:40:21 +00:00
Aadi Desai 1a413d9686 Merge branch 'main' into jl7719 2020-12-16 15:40:07 +00:00
jl7719 ebe33ce56a Passes all tests 2020-12-16 15:29:04 +00:00
Jeevaha Coelho 7185f7e7e6 Fixed BGEZAL 2020-12-16 07:00:46 -08:00
Aadi Desai 67682ecfde Create basic bus memory block 
I/O, parameters and initial setup block included
 2020-12-16 14:07:43 +00:00
Jeevaha Coelho 2673e23137 FIxed PC! 2020-12-16 05:21:57 -08:00
jl7719 ad68ab0974 Debugging and debugging 
PC, Jump instr, branches
 2020-12-16 12:29:22 +00:00
jl7719 0891f7e653 Debug mult/div to work 
it works now
 2020-12-16 08:38:46 +00:00
jl7719 4ff160db1a Fix syntax errors from mult/div 2020-12-16 05:04:45 +00:00
yhp19 07d32e9baf fixed input file plz document ur change in reference.txt 2020-12-16 12:27:48 +08:00
Jeevaha Coelho 864c8b6964 Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into jl7719 2020-12-15 13:48:50 -08:00
Jeevaha Coelho 90917f7566 Updated PC, Harv, ALU, to work w/ MULT(U), DIV(U) 2020-12-15 13:48:28 -08:00
yhp19 b54092cd57 reference txt 2020-12-16 01:00:03 +08:00
yhp19 cc5d2bbeab changes to input files 2020-12-16 00:57:46 +08:00
theexecutor13 6e600966db
Update reference.txt 2020-12-16 00:06:33 +08:00
jl7719 85efff275a Fix program counter taking two cycles for each instr 2020-12-15 15:53:30 +00:00
jl7719 01a3b9a973 Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into jl7719 
merge
 2020-12-15 15:20:43 +00:00
jl7719 fc5c8a17f5 Fix signed error in alu block 2020-12-15 15:19:51 +00:00
theexecutor13 44b6b7200f
Update reference.txt 2020-12-15 23:18:18 +08:00
jl7719 2e17e38957 Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into jl7719 
merge
 2020-12-15 15:07:22 +00:00
jl7719 b812399844 Fix to allow multiple testcases for each instruction 2020-12-15 15:06:04 +00:00
theexecutor13 c88ad413cf
Update reference.txt 2020-12-15 22:05:57 +08:00
Ibrahim adb4b5d6fd created seperate division testcases, fived srlv, sllu, srav & added sh (forgot this instruction previously) 2020-12-15 13:42:09 +00:00
Ibrahim 26ccff5057 Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into main 2020-12-15 13:38:04 +00:00
Jeevaha Coelho 85ba783a69 Fixed signing error in alu and added excel file 2020-12-15 05:21:37 -08:00
Jeevaha Coelho 5df8a72ca1 fixed naming convention errors in pc and harvard 2020-12-15 03:16:01 -08:00
ppuk 2030a186cc changed bltzal input txt 2020-12-15 08:56:23 +00:00
jl7719 63abcf671a Tidy up and change bash to ./ 2020-12-14 17:49:30 +00:00
jl7719 51dbe68ea8 Fix running on different environment issue 
Now completely shifted to Ubuntu 18.04 setup should work for everyone
 2020-12-14 17:38:39 +00:00
theexecutor13 6519be9a9e
Update reference.txt 2020-12-14 23:59:08 +08:00
theexecutor13 d72676c30c
Update bltzal.txt 2020-12-14 23:58:08 +08:00
ppuk 2d935d9211 linux supported 2020-12-14 15:38:05 +00:00
jc4419 da6be29109 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-13 15:38:04 +04:00
jc4419 be27fdc1ce Updated PC/Harvard, should work with delay slot 2020-12-13 15:37:44 +04:00
jl7719 f882d1e361 Test different inputs for lb, lbu 
it works
 2020-12-13 15:16:53 +09:00
jl7719 7150487472 Rename initialisation files 2020-12-13 14:54:53 +09:00
jl7719 943745a1e0 Tested all that can be tested for now 
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
 2020-12-13 14:40:16 +09:00
Aadi Desai 1123477690 Mask address during partial writes 2020-12-13 00:15:15 +00:00
Aadi Desai 50b9dba651 Added partial writes 
SH and SB were not accounted for in previous version, partial reads are handled within regfile
 2020-12-12 16:49:02 +00:00
jl7719 c31344c55f More testcases, testing, debugging 2020-12-13 01:25:36 +09:00
yhp19 276f7f8216 Added ref files for j and load instructions 2020-12-12 23:59:04 +08:00
yhp19 ab27fcaed3 Reference txt now in reference folders 2020-12-12 23:46:42 +08:00
yhp19 69cd711cfc Added load instruction txt and data.txt 2020-12-12 23:39:00 +08:00
jl7719 14ad7fa0ce Update program counter 
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
 2020-12-12 15:59:14 +09:00
Aadi Desai af7645b5b0 Completed wrapper, to be tested 2020-12-11 19:45:00 +00:00
Aadi Desai 714b74ec83 Update mips_cpu_bus.v 
Added fetch/execute states. All instructions not using data memory should function
 2020-12-11 19:13:11 +00:00