supleed2/ELEC40006-P1-CW
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Author SHA1 Message Date
Aadi Desai 3647e0b15c ALU now uses multiply block rather than * operator 
Updated to use custom block and decide which step of MUL, MLA and MLS depending on exec2 input
 2020-06-03 15:15:44 +01:00
Kacper 1c0032fa95 Fixed decoder and SM 2020-06-02 20:09:22 +01:00
Aadi Desai e1d7bf884d Merge branch 'master' of https://github.com/supleed2/CPUProject 2020-06-02 16:58:04 +01:00
Aadi Desai 2ca1e90a2c ALU enable control added, minor fix with RRC 
Multiply still to be updated
 2020-06-02 16:57:58 +01:00
ben 5d6c9803fc Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
Aadi Desai 3f0c91b0ff
Initial ALU Verilog 
Currently using incorrect implementation for Multiply (* operator), to be fixed once Multiply method is decided
 2020-05-29 14:16:02 +01:00
Benjamin Ramhorst fedfcaaada
Added most of the code for generating the instruction MIF. Still need to do a big if-else statement for every instruction. 2020-05-28 14:42:02 -07:00
ben 3d6e456fcc Almost completed 16 bit multiplier. 2020-05-28 15:02:22 -07:00
ben e39d2f653a Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
Kacper 132e1ad7fe
Delete DECODE.v.bak 2020-05-27 18:59:12 +01:00
Kacper cf179ad2cf Revisions for testing 2020-05-27 18:53:59 +01:00
Kacper e1acb56b66 Finished decoder 2020-05-27 18:53:03 +01:00
Kacper 1747e0c0b2 Delete cbx_args.txt 2020-05-27 11:10:59 +01:00
Kacper 5ed70dabb0 Working on datapath 2020-05-27 11:10:13 +01:00
Benjamin Ramhorst 9db1fb0af6 Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00
Kacper 3b298e02a2 Finished datapath 2020-05-25 18:00:34 +01:00
Kacper 6b2363d6a1 Working on initial design 2020-05-25 17:16:24 +01:00
Benjamin 14418c8725 VCS Test 2020-05-20 19:24:20 +01:00
Aadi Desai 26c28a829d Basic Project Setup 2020-05-20 12:44:57 +01:00
Aadi Desai 29cb9493a1
Add gitignore for quartus 2020-05-20 12:08:03 +01:00
Aadi Desai d86f15262c
Initial commit 2020-05-20 12:05:19 +01:00