supleed2/ELEC70056-HSV-CW2
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17 commits 1 branch 0 tags 3.8 MiB
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9 commits

Author SHA1 Message Date
Alden0012 8ae5a07fca add updated vga files 2022-12-16 22:11:31 +00:00
Alden0012 3c60629d48 Add scripts/rtl for formal verification 2022-12-16 20:19:07 +00:00
Aadi Desai 827ed444fa Fixes and adding missing setup.do script for vsim 2022-12-12 16:49:07 +00:00
Alden0012 aabd220e6a Increase covergroups and test inputs for VGA, Integrate gpio checker in tb 2022-12-12 16:16:17 +00:00
Alden0012 f586cd95d9 Add VGA and GPIO checker 2022-12-05 16:55:23 +00:00
Alden0012 f50d0c5c2e Add redundant VGA and comparator module 2022-11-08 17:49:23 +00:00
Aadi Desai 0d4099ce15 Update AHBVGASYS.sv to SystemVerilog and style 2022-11-07 13:57:19 +00:00
Aadi Desai c83b8a73f1 Switch all Verilog files to SystemVerilog file endings 2022-11-07 12:58:43 +00:00
Aadi Desai dcdda4d9e1 Initial Commit 2022-11-07 12:41:05 +00:00