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Author SHA1 Message Date
jl7719 f3779e1cc3 Fix div-5 testcase minor error 2020-12-18 09:24:58 +00:00
jl7719 2a7b9c2c49 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-18 09:22:27 +00:00
jl7719 47a452cd6d Fix div input testcases 3,4,5 2020-12-18 09:20:00 +00:00
ibzmo 339e2b6b58 updated ref 2020-12-18 09:15:58 +00:00
Ibrahim 579dc5e008 fixed one test case 2020-12-18 09:10:46 +00:00
Ibrahim c13ed23d90 ref file for these test cases - will add complete ref file for all edge cases soon 2020-12-18 08:51:53 +00:00
Ibrahim 48e0cdfbb6 added edge cases these don't pass - please check 2020-12-18 08:48:51 +00:00
Aadi Desai 099540f6ec
Merge pull request #2 from supleed2/bus_wrapper 
Merge Bus Version and updated testcases to Main
 2020-12-17 18:25:17 +00:00
Aadi Desai 1be11d6c19 Add second store halfword testcase 
Checks that only half the word is written using load word after store halfword
 2020-12-17 10:00:18 -08:00
Aadi Desai 5c29ec2be1 Shorten testbench limit, remove custom bus script 2020-12-17 09:44:31 -08:00
Aadi Desai e513096ed8 Add missing opcodes to CtrlMemRead = 0 2020-12-17 09:43:47 -08:00
Aadi Desai 6687cb8e17 Bring read signal low with clk during read cycle 2020-12-17 09:43:04 -08:00
Aadi Desai c8344184b2 Fix sb, sh testcases 
Tried to write to instr mem + typo
 2020-12-17 09:41:55 -08:00
Aadi Desai ad394c7d7d Adding missing opcodes to CtrlMemRead 2020-12-17 09:02:58 -08:00
Aadi Desai cb29efd034 Merge branch 'main' into bus_wrapper 2020-12-17 16:46:01 +00:00
Aadi Desai 2be1978a36 Add initial value to npc, add JR to CtrlMemRead 2020-12-17 08:43:58 -08:00
Aadi Desai 1ae5d78b4d Added dummy clk_enable to harvard instance, added clock kickstart after reset 2020-12-17 07:58:33 -08:00
Aadi Desai 74681e8890 Stall bus memory when reset is high 2020-12-17 07:34:32 -08:00
jl7719 cfebb403ba Delete from source files and the testbench 2020-12-17 15:02:59 +00:00
jl7719 2d9cca262d Fix display appearing at the end of log file 2020-12-17 14:51:08 +00:00
Aadi Desai e89087c127 Bus Memory typo in bus script 2020-12-17 06:34:42 -08:00
theexecutor13 6c400f3567 uploading log.txt weirdness testcase 2020-12-17 14:31:33 +00:00
Aadi Desai 2eccc5148e Move bus memory from rtl to testbench folder 2020-12-17 13:58:07 +00:00
Aadi Desai af29f22651 Merge branch 'main' into bus_wrapper 
Changes to be duplicated for bus version
 2020-12-17 13:54:26 +00:00
theexecutor13 0bdbb63f49
Update reference.txt 2020-12-17 21:37:17 +08:00
theexecutor13 7fcc2486cb cleanup 2020-12-17 13:37:00 +00:00
theexecutor13 ab13c84ef5 testing branch delay slot 2020-12-17 12:03:30 +00:00
theexecutor13 4ab4809a8a restructuring 2020-12-17 11:47:13 +00:00
theexecutor13 15dfce09c9
Update reference.txt 2020-12-17 19:44:23 +08:00
jl7719 6e626c5931 Change location of the memory module from rtl to testbench 2020-12-17 10:32:52 +00:00
Aadi Desai 33bb4c7538 Constant selects not working in always_ff in current iverilog 2020-12-16 14:21:26 -08:00
Aadi Desai 5e62dd82d8 Add bus vcd to gitignore, fix missing case in bus 2020-12-16 14:08:28 -08:00
Aadi Desai d17060b0a1 Add missing end to if statement 2020-12-16 13:54:01 -08:00
Aadi Desai da0c9aba01 Fix {} for bit duplication, remove module name from endmodule 2020-12-16 13:38:09 -08:00
Aadi Desai 744aee097f Modify bus tb to compile bus version instead 2020-12-16 20:15:08 +00:00
Aadi Desai 4534ca6760 Add custom test script for bus tb 
Bus specific testcases have been uncommented (sb, sh)
 2020-12-16 20:09:08 +00:00
Aadi Desai 2f9b08a363 Updated bus tb to match harvard tb 2020-12-16 20:05:00 +00:00
Aadi Desai a31ed073e1 Merge branch 'main' into bus_wrapper 2020-12-16 19:57:28 +00:00
Aadi Desai 20880f6ab2 Complete avalon bus memory 
Read and write logic (including partial writes using byte enables) complete. Address is always word aligned, as handled within bus wrapper.
 2020-12-16 19:20:48 +00:00
jl7719 697b6e0a9e Update some testcases for branch delay slots 2020-12-16 17:13:39 +00:00
jl7719 ec275418b7 Update harvard testbench regarding resets 2020-12-16 16:59:28 +00:00
jl7719 1f7027f771 Update harvard test script to match spec 
main branch ignore bus implementation
 2020-12-16 16:46:27 +00:00
Aadi Desai f5fea77ea7 General structure of bus memory 
Read and Write logic to be added
 2020-12-16 08:42:26 -08:00
jl7719 4be3149300 Update test_mips_cpu_bus.sh 
Needs checking for source file for bus version
 2020-12-16 15:58:03 +00:00
Aadi Desai d8c918c9b4 Merge branch 'main' into bus_wrapper 2020-12-16 15:41:56 +00:00
Aadi Desai 252f630162 Cleanup 2020-12-16 15:40:21 +00:00
Aadi Desai 1a413d9686 Merge branch 'main' into jl7719 2020-12-16 15:40:07 +00:00
jl7719 ebe33ce56a Passes all tests 2020-12-16 15:29:04 +00:00
Jeevaha Coelho 7185f7e7e6 Fixed BGEZAL 2020-12-16 07:00:46 -08:00
Aadi Desai 67682ecfde Create basic bus memory block 
I/O, parameters and initial setup block included
 2020-12-16 14:07:43 +00:00