37 commits

Author	SHA1	Message	Date
jl7719	a31d41512b	Rename all instruction mem init files to .instr.txt	2020-12-18 12:42:58 +00:00
jl7719	dd4f6346be	Add exec folder and executable.txt back for the test to work	2020-12-18 10:51:30 +00:00
jl7719	a4a28db189	Add stderr.txt files and diff.txt files for debugging	2020-12-18 10:41:01 +00:00
jl7719	4f97fb41d8	Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v	2020-12-18 09:55:41 +00:00
Aadi Desai	5c29ec2be1	Shorten testbench limit, remove custom bus script	2020-12-17 09:44:31 -08:00
Aadi Desai	cb29efd034	Merge branch 'main' into bus_wrapper	2020-12-17 16:46:01 +00:00
Aadi Desai	2be1978a36	Add initial value to npc, add JR to CtrlMemRead	2020-12-17 08:43:58 -08:00
jl7719	cfebb403ba	Delete from source files and the testbench	2020-12-17 15:02:59 +00:00
jl7719	2d9cca262d	Fix display appearing at the end of log file	2020-12-17 14:51:08 +00:00
Aadi Desai	e89087c127	Bus Memory typo in bus script	2020-12-17 06:34:42 -08:00
Aadi Desai	2eccc5148e	Move bus memory from rtl to testbench folder	2020-12-17 13:58:07 +00:00
Aadi Desai	af29f22651	Merge branch 'main' into bus_wrapper ... Changes to be duplicated for bus version	2020-12-17 13:54:26 +00:00
jl7719	6e626c5931	Change location of the memory module from rtl to testbench	2020-12-17 10:32:52 +00:00
Aadi Desai	33bb4c7538	Constant selects not working in always_ff in current iverilog	2020-12-16 14:21:26 -08:00
Aadi Desai	da0c9aba01	Fix {} for bit duplication, remove module name from endmodule	2020-12-16 13:38:09 -08:00
Aadi Desai	744aee097f	Modify bus tb to compile bus version instead	2020-12-16 20:15:08 +00:00
Aadi Desai	4534ca6760	Add custom test script for bus tb ... Bus specific testcases have been uncommented (sb, sh)	2020-12-16 20:09:08 +00:00
Aadi Desai	a31ed073e1	Merge branch 'main' into bus_wrapper	2020-12-16 19:57:28 +00:00
jl7719	1f7027f771	Update harvard test script to match spec ... main branch ignore bus implementation	2020-12-16 16:46:27 +00:00
jl7719	4be3149300	Update test_mips_cpu_bus.sh ... Needs checking for source file for bus version	2020-12-16 15:58:03 +00:00
jl7719	ebe33ce56a	Passes all tests	2020-12-16 15:29:04 +00:00
jl7719	ad68ab0974	Debugging and debugging ... PC, Jump instr, branches	2020-12-16 12:29:22 +00:00
jl7719	0891f7e653	Debug mult/div to work ... it works now	2020-12-16 08:38:46 +00:00
jl7719	b812399844	Fix to allow multiple testcases for each instruction	2020-12-15 15:06:04 +00:00
jl7719	63abcf671a	Tidy up and change bash to ./	2020-12-14 17:49:30 +00:00
jl7719	51dbe68ea8	Fix running on different environment issue ... Now completely shifted to Ubuntu 18.04 setup should work for everyone	2020-12-14 17:38:39 +00:00
ppuk	2d935d9211	linux supported	2020-12-14 15:38:05 +00:00
jl7719	7150487472	Rename initialisation files	2020-12-13 14:54:53 +09:00
jl7719	943745a1e0	Tested all that can be tested for now ... Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus	2020-12-13 14:40:16 +09:00
jl7719	c31344c55f	More testcases, testing, debugging	2020-12-13 01:25:36 +09:00
jl7719	14ad7fa0ce	Update program counter ... Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register	2020-12-12 15:59:14 +09:00
jl7719	3594365a25	Create branch jl7719 ... Can test for normal pc incrementing instr	2020-12-11 19:45:13 +09:00
jl7719	c93473a54d	Update test_mips_cpu_harvard.sh ... Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)	2020-12-10 17:24:40 +09:00
jl7719	c5aed43ab4	Update to test each instruction with a small memory	2020-12-09 16:47:58 +09:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
jl7719	411f89110f	Add testbench related files	2020-12-04 23:44:48 +09:00
jl7719	e6e4f17afe	Add initial coursework deliverables	2020-11-24 14:20:29 +09:00