supleed2/ELEC50010-IAC-CW
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189 commits 2 branches 0 tags 9.2 MiB
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21 commits

Author SHA1 Message Date
Aadi Desai 088b2bae21 Replace .v with .sv in scripts to match 2020-12-19 08:43:28 -08:00
jl7719 a59e73f746 Fix test script not being able to find src dir 
Bus fixed in previous commit
 2020-12-18 12:51:53 +00:00
jl7719 a31d41512b Rename all instruction mem init files to .instr.txt 2020-12-18 12:42:58 +00:00
jl7719 dd4f6346be Add exec folder and executable.txt back for the test to work 2020-12-18 10:51:30 +00:00
jl7719 a4a28db189 Add stderr.txt files and diff.txt files for debugging 2020-12-18 10:41:01 +00:00
jl7719 4f97fb41d8 Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v 2020-12-18 09:55:41 +00:00
Aadi Desai af29f22651 Merge branch 'main' into bus_wrapper 
Changes to be duplicated for bus version
 2020-12-17 13:54:26 +00:00
jl7719 1f7027f771 Update harvard test script to match spec 
main branch ignore bus implementation
 2020-12-16 16:46:27 +00:00
jl7719 b812399844 Fix to allow multiple testcases for each instruction 2020-12-15 15:06:04 +00:00
jl7719 51dbe68ea8 Fix running on different environment issue 
Now completely shifted to Ubuntu 18.04 setup should work for everyone
 2020-12-14 17:38:39 +00:00
ppuk 2d935d9211 linux supported 2020-12-14 15:38:05 +00:00
jl7719 7150487472 Rename initialisation files 2020-12-13 14:54:53 +09:00
jl7719 943745a1e0 Tested all that can be tested for now 
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
 2020-12-13 14:40:16 +09:00
jl7719 c31344c55f More testcases, testing, debugging 2020-12-13 01:25:36 +09:00
jl7719 14ad7fa0ce Update program counter 
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
 2020-12-12 15:59:14 +09:00
jl7719 3594365a25 Create branch jl7719 
Can test for normal pc incrementing instr
 2020-12-11 19:45:13 +09:00
jl7719 c93473a54d Update test_mips_cpu_harvard.sh 
Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)
 2020-12-10 17:24:40 +09:00
jl7719 c5aed43ab4 Update to test each instruction with a small memory 2020-12-09 16:47:58 +09:00
jl7719 c5167645e7 Fix overall w.r.t iverilog compiler error 2020-12-06 15:44:58 +09:00
jl7719 411f89110f Add testbench related files 2020-12-04 23:44:48 +09:00
jl7719 e6e4f17afe Add initial coursework deliverables 2020-11-24 14:20:29 +09:00