16 commits

Author	SHA1	Message	Date
Jeevaha Coelho	7185f7e7e6	Fixed BGEZAL	2020-12-16 07:00:46 -08:00
jl7719	0891f7e653	Debug mult/div to work ... it works now	2020-12-16 08:38:46 +00:00
jl7719	85efff275a	Fix program counter taking two cycles for each instr	2020-12-15 15:53:30 +00:00
jl7719	7150487472	Rename initialisation files	2020-12-13 14:54:53 +09:00
jl7719	943745a1e0	Tested all that can be tested for now ... Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus	2020-12-13 14:40:16 +09:00
jl7719	c31344c55f	More testcases, testing, debugging	2020-12-13 01:25:36 +09:00
jl7719	3594365a25	Create branch jl7719 ... Can test for normal pc incrementing instr	2020-12-11 19:45:13 +09:00
jl7719	7ffd8fb400	Add testcases and ref outputs for addiu, and, andi	2020-12-11 15:17:43 +09:00
jl7719	04b1ed4fed	Update control and memory ... Fixed some errors when testing	2020-12-10 22:27:08 +09:00
jl7719	84adff2ed1	Update memory ... No longer need the massive memory	2020-12-10 19:14:16 +09:00
jl7719	c5aed43ab4	Update to test each instruction with a small memory	2020-12-09 16:47:58 +09:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
jl7719	411f89110f	Add testbench related files	2020-12-04 23:44:48 +09:00
jl7719	10af46a352	Update mips_cpu_memory.v	2020-12-02 23:41:04 +09:00
jl7719	841081c152	Update mips_cpu_memory.v ... Change as per constraint	2020-11-29 17:44:08 +09:00
jl7719	7c9fc23f7e	Update mips_cpu_data_memory.v to mips_cpu_memory.v	2020-11-29 17:06:18 +09:00