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943745a1e0
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
75 lines
2.6 KiB
Verilog
75 lines
2.6 KiB
Verilog
module mips_cpu_memory(
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input logic clk,
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//Data Memory
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input logic[31:0] data_address,
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input logic data_write,
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input logic data_read,
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input logic[31:0] data_writedata,
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output logic[31:0] data_readdata,
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//Instruction Memory
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input logic[31:0] instr_address,
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output logic[31:0] instr_readdata
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);
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parameter RAM_INIT_FILE = "";
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parameter MEM_INIT_FILE = "";
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reg [31:0] data_memory [0:31];
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reg [31:0] instr_memory [0:31];
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initial begin
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integer i;
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//Initialise to zero by default
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for (i=0; i<$size(data_memory); i++) begin
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data_memory[i] = 0;
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end
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for (i=0; i<$size(instr_memory); i++) begin
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instr_memory[i] = 0;
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end
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//Load contents from file if specified
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if (RAM_INIT_FILE != "") begin
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$display("RAM: Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, instr_memory);
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end
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for (integer j = 0; j<$size(instr_memory); j++) begin
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$display("byte +%h: %h", 32'hBFC00000+j*4, instr_memory[j]);
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end
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if (MEM_INIT_FILE != "") begin
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$display("MEM: Loading MEM contents from %s", MEM_INIT_FILE);
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$readmemh(MEM_INIT_FILE, data_memory);
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end else begin
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$display("MEM FILE NOT GIVEN");
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end
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for (integer k = 0; k<$size(data_memory); k++) begin
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$display("byte +%h: %h", 32'h00001000+k*4, data_memory[k]);
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end
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end
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//Combinatorial read path for data and instruction.
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assign data_readdata = data_read ? data_memory[(data_address-32'h00001000)>>2] : 32'hxxxxxxxx;
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assign instr_readdata = (instr_address >= 32'hBFC00000 && instr_address < 32'hBFC00000+$size(instr_memory)) ? instr_memory[(instr_address-32'hBFC00000)>>2] : 32'hxxxxxxxx;
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//Synchronous write path
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always_ff @(posedge clk) begin
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$display("Instruction Read: %h", instr_readdata);
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//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (data_write) begin //cannot read and write to memory in the same cycle
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if (instr_address != data_address) begin //cannot modify the instruction being read
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data_memory[(data_address-32'h00001000)>>2] <= data_writedata;
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$display("Store in memory");
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$display(data_writedata);
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end
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for (integer k = 0; k<$size(data_memory); k++) begin
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$display("byte +%h: %h", 32'h00001000+k*4, data_memory[k]);
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end
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end
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end
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endmodule
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