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72 lines
2.6 KiB
Verilog
72 lines
2.6 KiB
Verilog
/*
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Memory for Harvard Interface
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- RAM Size: 32 x 2^32 = 32 x 4294967296
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- Instructions in binaries or hex -> RAM_INIT_FILE
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- combinatorial read/fetch of instruction via instr_ port
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- combinatorial read and single cycle write of data via data_ port
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Instantiation of Memory Module
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- mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
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Special Memory Locations
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- Whether a particular address maps to RAM, ROM, or something else is entirely down to the top-level circuit outside your CPU.
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- special memory locations: 0x00000000 (CPU halt), 0xBFC00000 (start execution after reset)
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- PC should be 0xBFC00000 at the start and 0x00000000 at the end
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*/
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module mips_cpu_memory(
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input logic clk,
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//Data Memory
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input logic[31:0] data_address,
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input logic data_write,
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input logic data_read,
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input logic[31:0] data_writedata,
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output logic[31:0] data_readdata,
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//Instruction Memory
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input logic[31:0] instr_address,
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output logic[31:0] instr_readdata
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);
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parameter RAM_INIT_FILE = "";
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reg [31:0] memory [0:7]; // 2^30 set as 8 for now for small testcases
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initial begin
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integer i;
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//Initialise to zero by default
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for (i=0; i<8; i++) begin
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memory[i]=0;
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end
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//Load contents from file if specified
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if (RAM_INIT_FILE != "") begin
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$display("RAM: Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory, 32'h4); //32'hBFC00000 equivalent for small memory as byte 16
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end
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//Display what's in memory for debugging
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for (integer j = 0; j<$size(memory); j++) begin
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$display("Byte %d, %h", j*4, memory[j]);
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end
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end
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//Combinatorial read path for data and instruction.
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assign data_readdata = data_read ? {memory[data_address],memory[data_address+1],memory[data_address+2],memory[data_address+3]} : 16'hxxxx;
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assign instr_readdata = memory[instr_address/4];
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//Synchronous write path
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always_ff @(posedge clk) begin
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$display("Instruction Read: %h", instr_readdata);
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//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
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if (instr_address != data_address) begin //cannot modify the instruction being read
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memory[data_address] <= data_writedata;
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end
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end
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end
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endmodule
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