Aadi Desai
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6637ad813f
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Rename vcd to differentiate between bus and harvard
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2020-12-20 08:46:29 -08:00 |
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Aadi Desai
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859020bae5
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Add testcase specific waveforms
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2020-12-20 08:42:37 -08:00 |
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jl7719
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a59e73f746
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Fix test script not being able to find src dir
Bus fixed in previous commit
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2020-12-18 12:51:53 +00:00 |
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jl7719
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a31d41512b
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Rename all instruction mem init files to .instr.txt
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2020-12-18 12:42:58 +00:00 |
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jl7719
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dd4f6346be
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Add exec folder and executable.txt back for the test to work
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2020-12-18 10:51:30 +00:00 |
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jl7719
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a4a28db189
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Add stderr.txt files and diff.txt files for debugging
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2020-12-18 10:41:01 +00:00 |
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jl7719
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4f97fb41d8
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Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v
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2020-12-18 09:55:41 +00:00 |
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Aadi Desai
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5c29ec2be1
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Shorten testbench limit, remove custom bus script
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2020-12-17 09:44:31 -08:00 |
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Aadi Desai
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cb29efd034
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Merge branch 'main' into bus_wrapper
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2020-12-17 16:46:01 +00:00 |
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Aadi Desai
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2be1978a36
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Add initial value to npc, add JR to CtrlMemRead
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2020-12-17 08:43:58 -08:00 |
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jl7719
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cfebb403ba
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Delete from source files and the testbench
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2020-12-17 15:02:59 +00:00 |
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jl7719
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2d9cca262d
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Fix display appearing at the end of log file
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2020-12-17 14:51:08 +00:00 |
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Aadi Desai
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e89087c127
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Bus Memory typo in bus script
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2020-12-17 06:34:42 -08:00 |
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Aadi Desai
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2eccc5148e
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Move bus memory from rtl to testbench folder
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2020-12-17 13:58:07 +00:00 |
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Aadi Desai
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af29f22651
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Merge branch 'main' into bus_wrapper
Changes to be duplicated for bus version
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2020-12-17 13:54:26 +00:00 |
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jl7719
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6e626c5931
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Change location of the memory module from rtl to testbench
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2020-12-17 10:32:52 +00:00 |
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Aadi Desai
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33bb4c7538
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Constant selects not working in always_ff in current iverilog
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2020-12-16 14:21:26 -08:00 |
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Aadi Desai
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da0c9aba01
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Fix {} for bit duplication, remove module name from endmodule
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2020-12-16 13:38:09 -08:00 |
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Aadi Desai
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744aee097f
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Modify bus tb to compile bus version instead
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2020-12-16 20:15:08 +00:00 |
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Aadi Desai
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4534ca6760
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Add custom test script for bus tb
Bus specific testcases have been uncommented (sb, sh)
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2020-12-16 20:09:08 +00:00 |
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Aadi Desai
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a31ed073e1
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Merge branch 'main' into bus_wrapper
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2020-12-16 19:57:28 +00:00 |
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jl7719
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1f7027f771
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Update harvard test script to match spec
main branch ignore bus implementation
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2020-12-16 16:46:27 +00:00 |
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jl7719
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4be3149300
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Update test_mips_cpu_bus.sh
Needs checking for source file for bus version
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2020-12-16 15:58:03 +00:00 |
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jl7719
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ebe33ce56a
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Passes all tests
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2020-12-16 15:29:04 +00:00 |
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jl7719
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ad68ab0974
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Debugging and debugging
PC, Jump instr, branches
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2020-12-16 12:29:22 +00:00 |
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jl7719
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0891f7e653
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Debug mult/div to work
it works now
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2020-12-16 08:38:46 +00:00 |
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jl7719
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b812399844
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Fix to allow multiple testcases for each instruction
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2020-12-15 15:06:04 +00:00 |
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jl7719
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63abcf671a
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Tidy up and change bash to ./
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2020-12-14 17:49:30 +00:00 |
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jl7719
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51dbe68ea8
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Fix running on different environment issue
Now completely shifted to Ubuntu 18.04 setup should work for everyone
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2020-12-14 17:38:39 +00:00 |
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ppuk
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2d935d9211
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linux supported
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2020-12-14 15:38:05 +00:00 |
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jl7719
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7150487472
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Rename initialisation files
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2020-12-13 14:54:53 +09:00 |
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jl7719
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943745a1e0
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Tested all that can be tested for now
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
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2020-12-13 14:40:16 +09:00 |
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jl7719
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c31344c55f
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More testcases, testing, debugging
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2020-12-13 01:25:36 +09:00 |
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jl7719
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14ad7fa0ce
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Update program counter
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
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2020-12-12 15:59:14 +09:00 |
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jl7719
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3594365a25
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Create branch jl7719
Can test for normal pc incrementing instr
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2020-12-11 19:45:13 +09:00 |
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jl7719
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c93473a54d
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Update test_mips_cpu_harvard.sh
Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)
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2020-12-10 17:24:40 +09:00 |
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jl7719
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c5aed43ab4
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Update to test each instruction with a small memory
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2020-12-09 16:47:58 +09:00 |
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jl7719
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c5167645e7
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Fix overall w.r.t iverilog compiler error
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2020-12-06 15:44:58 +09:00 |
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jl7719
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411f89110f
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Add testbench related files
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2020-12-04 23:44:48 +09:00 |
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jl7719
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e6e4f17afe
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Add initial coursework deliverables
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2020-11-24 14:20:29 +09:00 |
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