jl7719
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2d9cca262d
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Fix display appearing at the end of log file
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2020-12-17 14:51:08 +00:00 |
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jl7719
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6e626c5931
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Change location of the memory module from rtl to testbench
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2020-12-17 10:32:52 +00:00 |
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jl7719
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ec275418b7
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Update harvard testbench regarding resets
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2020-12-16 16:59:28 +00:00 |
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jl7719
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7150487472
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Rename initialisation files
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2020-12-13 14:54:53 +09:00 |
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jl7719
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943745a1e0
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Tested all that can be tested for now
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
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2020-12-13 14:40:16 +09:00 |
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jl7719
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3594365a25
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Create branch jl7719
Can test for normal pc incrementing instr
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2020-12-11 19:45:13 +09:00 |
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jl7719
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c5aed43ab4
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Update to test each instruction with a small memory
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2020-12-09 16:47:58 +09:00 |
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Ibrahim
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11cabd3aea
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changing module name
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2020-12-07 10:52:01 +00:00 |
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jl7719
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c5167645e7
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Fix overall w.r.t iverilog compiler error
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2020-12-06 15:44:58 +09:00 |
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jl7719
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411f89110f
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Add testbench related files
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2020-12-04 23:44:48 +09:00 |
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