9 commits

Author	SHA1	Message	Date
jl7719	6e626c5931	Change location of the memory module from rtl to testbench	2020-12-17 10:32:52 +00:00
jl7719	ec275418b7	Update harvard testbench regarding resets	2020-12-16 16:59:28 +00:00
jl7719	7150487472	Rename initialisation files	2020-12-13 14:54:53 +09:00
jl7719	943745a1e0	Tested all that can be tested for now ... Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus	2020-12-13 14:40:16 +09:00
jl7719	3594365a25	Create branch jl7719 ... Can test for normal pc incrementing instr	2020-12-11 19:45:13 +09:00
jl7719	c5aed43ab4	Update to test each instruction with a small memory	2020-12-09 16:47:58 +09:00
Ibrahim	11cabd3aea	changing module name	2020-12-07 10:52:01 +00:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
jl7719	411f89110f	Add testbench related files	2020-12-04 23:44:48 +09:00