Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London
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2023-06-26 14:10:40 +01:00
demo Visualise IRQ via LED 2023-06-10 15:18:42 +01:00
modules Tidy project 2023-06-18 17:25:53 +01:00
notes Add Sine 440Hz Images 2023-06-26 14:10:40 +01:00
rtl Tidy project 2023-06-18 17:25:53 +01:00
.gitignore Tidy project 2023-06-18 17:25:53 +01:00
.svlint.toml Clean up .svlint.toml 2023-05-18 12:34:03 +01:00
build.sh Switch from vexriscv to picorv32 2023-06-10 14:08:56 +01:00
make.py Tidy project 2023-06-18 17:25:53 +01:00
readme.md Extra links for CPU change / FreeRTOS 2023-06-10 16:54:38 +01:00
Writeup.docx Save Writeup files and add all images and diagrams 2023-06-24 11:53:53 +01:00
writeup.md Save Writeup files and add all images and diagrams 2023-06-24 11:53:53 +01:00
Writeup.pdf Save Writeup files and add all images and diagrams 2023-06-24 11:53:53 +01:00

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