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Save Writeup files and add all images and diagrams
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Writeup.docx
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Writeup.docx
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Writeup.pdf
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Writeup.pdf
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notes/CANdecoder.png
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notes/CANdecoder.png
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notes/ata6561.png
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notes/ata6561.png
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notes/audioInputFormats.png
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notes/canAck.png
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notes/canAck.png
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notes/canArbitration.png
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notes/canArbitration.png
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notes/canFrame.png
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notes/canFrame.png
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notes/cleanwave.png
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notes/cleanwave.png
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notes/controlInterfaceTiming.png
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notes/controlInterfaceTiming.png
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notes/glitchingwave.png
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notes/glitchingwave.png
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notes/glitchmask.png
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notes/glitchmask.png
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notes/gtkwaveAsyncfifo.png
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notes/gtkwaveAsyncfifo.png
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notes/gtkwaveAsyncfifo.vcd
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notes/gtkwaveAsyncfifo.vcd
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notes/gtkwaveDacdriver.png
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notes/gtkwaveDacdriver.png
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notes/gtkwaveDacdriver.vcd
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notes/gtkwaveDacdriver.vcd
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notes/perfOrangeCrab.png
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notes/perfStackSynth.png
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notes/sampleGenerator.drawio
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notes/sampleGenerator.drawio
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notes/sampleGenerator.png
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notes/sampleGenerator.png
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notes/signedsine.png
Normal file
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notes/signedsine.png
Normal file
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@ -223,7 +223,7 @@
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@ -231,26 +231,26 @@
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<mxCell id="hBXv7jzEsvArLMJGQopC-82" value="bck" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=1;exitY=0.75;exitDx=0;exitDy=0;entryX=0.25;entryY=0;entryDx=0;entryDy=0;fontSize=11;" parent="1" source="hBXv7jzEsvArLMJGQopC-81" target="hBXv7jzEsvArLMJGQopC-70" edge="1">
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@ -258,20 +258,20 @@
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<mxPoint as="offset" />
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<mxCell id="hBXv7jzEsvArLMJGQopC-81" value="DAC Driver" style="whiteSpace=wrap;html=1;fontSize=11;fillColor=#d5e8d4;strokeColor=#82b366;" parent="1" vertex="1">
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@ -280,7 +280,7 @@
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<mxGeometry relative="1" as="geometry">
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@ -289,60 +289,60 @@
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<mxPoint x="200" y="29.83" as="sourcePoint" />
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<mxPoint x="220" y="29.83" as="targetPoint" />
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<mxPoint x="30" y="30" as="offset" />
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</mxGeometry>
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</mxCell>
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<mxCell id="hBXv7jzEsvArLMJGQopC-117" value="Bus" style="endArrow=none;html=1;rounded=0;strokeWidth=2;fontSize=11;" edge="1" parent="1">
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<mxPoint x="290" y="9.999999999999998" as="targetPoint" />
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<mxPoint x="20" y="20" as="offset" />
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<mxGeometry relative="1" as="geometry">
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</mxGeometry>
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</mxCell>
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<mxCell id="hBXv7jzEsvArLMJGQopC-34" value="clk" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.25;entryDx=0;entryDy=0;fontSize=11;" edge="1" parent="1" target="hBXv7jzEsvArLMJGQopC-32">
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<mxCell id="hBXv7jzEsvArLMJGQopC-34" value="clk" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.25;entryDx=0;entryDy=0;fontSize=11;" parent="1" target="hBXv7jzEsvArLMJGQopC-32" edge="1">
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<Array as="points">
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|
@ -352,12 +352,12 @@
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<mxPoint as="offset" />
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<mxCell id="hBXv7jzEsvArLMJGQopC-14" value="clk" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.25;entryDx=0;entryDy=0;fontSize=11;" edge="1" parent="1" target="hBXv7jzEsvArLMJGQopC-13">
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<mxCell id="hBXv7jzEsvArLMJGQopC-14" value="clk" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.25;entryDx=0;entryDy=0;fontSize=11;" parent="1" target="hBXv7jzEsvArLMJGQopC-13" edge="1">
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<mxPoint x="360" y="100" as="sourcePoint" />
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<Array as="points">
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|
@ -367,12 +367,12 @@
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<mxPoint as="offset" />
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</mxCell>
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</root>
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BIN
notes/systemOverview.png
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notes/systemOverview.png
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|
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notes/testPropTiming.png
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notes/testPropTiming.png
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|
After Width: | Height: | Size: 13 KiB |
BIN
notes/unsignedsine.png
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notes/unsignedsine.png
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|
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|
Before Width: | Height: | Size: 1.1 MiB |
28
writeup.md
28
writeup.md
|
|
@ -20,7 +20,9 @@ Standard Template is on Intranet
|
|||
|
||||
# Acknowledgements
|
||||
|
||||
I would like to thank Dr Ed Stott for his time and patience in the many meetings it took to discuss this project, as well as his guidance in architectural decisions that impacted the entire project. Without this insight, much more time may have been spend investigating alternatives and this project may not have reached a Proof-of-Concept stage that is useful for future students of the 3rd Year Embedded Systems module..
|
||||
I would like to thank Dr Ed Stott for his time and patience in the many meetings it took to discuss this project, as well as his guidance in architectural decisions that impacted the entire project. Without this insight, much more time may have been spend investigating alternatives and this project may not have reached a Proof-of-Concept stage that is useful for future students of the 3rd Year Embedded Systems module.
|
||||
|
||||
I would also like to thank my friends and family for their support and encouragement throughout the project, especially my peers who stayed up late with me as we worked on our projects together.
|
||||
|
||||
# Abstract
|
||||
|
||||
|
|
@ -82,10 +84,16 @@ The API for controlling the custom SystemVerilog logic has been designed to be s
|
|||
|
||||
# List of Figures
|
||||
|
||||
TODO
|
||||
|
||||
# List of Listings
|
||||
|
||||
TODO
|
||||
|
||||
# List of Tables
|
||||
|
||||
TODO
|
||||
|
||||
# List of Abbreviations
|
||||
|
||||
- ACM: Abstract Control Model (USB Class)
|
||||
|
|
@ -137,7 +145,7 @@ The report is structured as follows:
|
|||
- **Chapter 4 - Implementation** - Details the design decisions made during development and features of the project as completed
|
||||
- **Chapter 5 - Testing and Results** - Covers testing throughout the project used to verify functional correctness of the design and measure performance
|
||||
- **Chapter 6 - Evaluation** - Evaluates the project on progress against the identified objectives and areas that can be improved
|
||||
- **Chapter 7 - Conclusion** - Concludes the project, including insights into future work
|
||||
- **Chapter 7 - Conclusions** - Concludes the project, including insights into future work
|
||||
|
||||
# Background
|
||||
|
||||
|
|
@ -305,7 +313,7 @@ The CAN protocol is a NRZ (Non Return-to-Zero) protocol, meaning consecutive bit
|
|||
|
||||
[Listing: Bit stuffing example]
|
||||
|
||||
$0000011110 \rightarrow 00000\textcolor{red}{1}1111\textcolor{red}{0}0$
|
||||
$0000011110 \rightarrow 00000{red}{1}1111{red}{0}0$
|
||||
|
||||
A complete CAN bus frame is shown in Figure x.y, from the [Wikipedia page on the CAN bus](https://en.wikipedia.org/wiki/CAN_bus), where the frame ID is 0x14 and the frame contains 1 byte of data. In the case of the StackSynth module, the data length is hardcoded to 8 bytes within the CAN helper library, with unused bytes being ignored by the receiving device.
|
||||
|
||||
|
|
@ -1062,16 +1070,16 @@ fatal error: gnu/stubs-ilp32.h: No such file or directory
|
|||
8 | # include <gnu/stubs-ilp32.h>
|
||||
```
|
||||
|
||||
- TODO: Measure SNR and fill in
|
||||
And finally, a measure of the performance improvement in audio quality between the StackSynth and FPGA Extension boards is the SNR (Signal-to-Noise Ratio) of the audio output as a higher SNR would result in a lower noise floor and clearer audio for the same signal amplitude. Table x.y contains the frequency, SNR and THD results for the StackSynth board and the FPGA Extension board when using a target frequency of 3520Hz (A7), each using 500 samples in the measurement. The screenshots of the PicoScope measurements are included in Appendix x.y.
|
||||
|
||||
Finally, a useful measure of the performance improvement in audio quality between the StackSynth and FPGA Extension boards is the SNR (Signal-to-Noise Ratio) of the audio output as a higher SNR would result in a lower noise floor and clearer audio. As shown in Table x.y, the average measured SNR of the StackSynth board was ??.? dB and of the FPGA Extension board was ??.? dB, showing a significant improvement in audio quality. The screenshots of the PicoScope measurements are included in Appendix x.y.
|
||||
The results show a small but measurable improvement in SND as well as THD, while the frequency is slightly further from the target on the FPGA. Overall the audio performance of a single oscillator is similar, however the FPGA accelerator is capable of many more oscillators simultaneously.
|
||||
|
||||
[Table: SNR of StackSynth and FPGA Extension boards]
|
||||
[Table: SNR and THD of StackSynth and FPGA Extension boards]
|
||||
|
||||
| Board | SNR (dB) |
|
||||
| -------------- | -------- |
|
||||
| StackSynth | ??.?? |
|
||||
| FPGA Extension | ??.?? |
|
||||
| Board | Frequency (Hz) | SNR (dBc) | THD (%) |
|
||||
| -------------- | -------------- | --------- | ------- |
|
||||
| StackSynth | 3520.29 | 24.48 | 2.71 |
|
||||
| FPGA Extension | 3520.60 | 25.18 | 2.12 |
|
||||
|
||||
# Evaluation
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue