Tidy project

Rename modules for clarity
Move LiteX modules into `modules/`
Move extras into `notes/`

.gitignore

@@ -1,7 +1,7 @@
 /.vscode/
 /build/
 /docs/
-/__pycache__/
+__pycache__/
 /demo/*.o
 /demo/*.d
 /demo/demo.bin

make.py

@@ -194,7 +194,7 @@ class BaseSoC(SoCCore):
             #     pads         = platform.request_all("user_led"),
             #     sys_clk_freq = sys_clk_freq
             # )
-            from testRGB import TestRgb
+            from modules.testRGB import TestRgb
             self.leds = TestRgb(
                 platform = platform,
                 pads     = platform.request_all("user_led")
@@ -228,7 +228,7 @@ class BaseSoC(SoCCore):
         ])
 
         # CAN Receiver Block -----------------------------------------------------------------------
-        from testCAN import CanReceiver
+        from modules.canReceiver import CanReceiver
         self.can = CanReceiver(
             platform = platform,
             pads     = platform.request("can")
@@ -236,25 +236,20 @@ class BaseSoC(SoCCore):
         self.irq.add("can", use_loc_if_exists=True)
 
         # DAC Control / Audio Blocks ---------------------------------------------------------------
-        from testWave import TestWave
-        self.audio = TestWave(
+        from modules.genWave import GenerateWave
+        self.audio = GenerateWave(
             platform = platform,
             pads     = platform.request("dac_pcm")
         )
-        # from testSaw import TestSaw
-        # self.audio = TestSaw(
-        #     platform = platform,
-        #     pads     = platform.request("dac_pcm")
-        # )
-        # from dacVolume import DacVolume
-        # self.dac_vol = DacVolume(
+        # from modules.dacAttenuation import DacAttenuation
+        # self.dac_atten = DacAttenuation(
         #     platform = platform,
         #     pads     = platform.request("dac_ctrl")
         # )
 
         # Propagation Delay Test -------------------------------------------------------------------
-        # from testProp import TestProp
-        # self.proptest = TestProp(platform = platform)
+        # from modules.testPropagation import TestPropagation
+        # self.proptest = TestPropagation(platform = platform)
 
         # LiteScope Analyzer -----------------------------------------------------------------------
         self.add_uartbone(name="debug_uart", baudrate=921600)
@@ -264,11 +259,11 @@ class BaseSoC(SoCCore):
             # self.proptest.o_sin,
             self.can.can_rx,
             self.can.can_tx,
-            # self.dac_vol.volume.re,
-            # self.dac_vol.volume.storage,
-            # self.dac_vol.m_sel_n,
-            # self.dac_vol.m_clock,
-            # self.dac_vol.m_data,
+            # self.dac_atten.atten.re,
+            # self.dac_atten.atten.storage,
+            # self.dac_atten.m_sel_n,
+            # self.dac_atten.m_clock,
+            # self.dac_atten.m_data,
             self.audio.osc.re,
             # self.audio.osc.storage,
             self.audio.tf.re,

modules/dacAttenuation.py

@@ -5,17 +5,17 @@ from litex.soc.integration.doc import ModuleDoc
 
 # Test RGB Module ----------------------------------------------------------------------------------
 
-class DacVolume(Module, AutoCSR, ModuleDoc):
+class DacAttenuation(Module, AutoCSR, ModuleDoc):
     """
-    DAC Volume Control Module
+    DAC Attenuation Control Module
 
     Set the Attenuation of the PCM1780 DAC
     """
     def __init__(self, platform, pads):
-        platform.add_source("rtl/dacVolume.sv")
+        platform.add_source("rtl/dacAttenuation.sv")
 
         self.pads = pads
-        self.volume = CSRStorage(size = 8, reset = 128, description = "PCM1780: Attenuation Control")
+        self.atten = CSRStorage(size = 8, reset = 128, description = "PCM1780: Attenuation Control")
 
         self.m_sel_n = Signal()
         self.m_clock = Signal()
@@ -23,11 +23,11 @@ class DacVolume(Module, AutoCSR, ModuleDoc):
 
         # # #
 
-        self.specials += Instance("dacVolume",
+        self.specials += Instance("dacAttenuation",
             i_i_clk48   = ClockSignal(),
             i_i_rst48_n = ~ResetSignal(),
-            i_i_valid   = self.volume.re,
-            i_i_volume  = self.volume.storage,
+            i_i_valid   = self.atten.re,
+            i_i_atten   = self.atten.storage,
             o_o_sel_n   = self.m_sel_n,
             o_o_clock   = self.m_clock,
             o_o_data    = self.m_data,

modules/genWave.py

@@ -4,13 +4,12 @@ from litex.soc.interconnect.csr import *
 from migen.genlib.fifo import AsyncFIFO as MigenAsyncFIFO
 from litex.soc.integration.doc import ModuleDoc
 
-# Test RGB Module ----------------------------------------------------------------------------------
-
-class TestWave(Module, AutoCSR, ModuleDoc):
+class GenerateWave(Module, AutoCSR, ModuleDoc):
     """
-    Multi Wave Test Module
+    Multi Wave Generation Module
 
     Set the target frequency and waveform outpput for each of 128 oscillators.
+    Outputs samples normalised in range 0.5-1x max amplitude.
     """
     def __init__(self, platform, pads):
         platform.add_source("rtl/cordic.sv")

modules/testPropagation.py

@@ -5,7 +5,7 @@ from litex.soc.integration.doc import ModuleDoc
 
 # Test RGB Module ----------------------------------------------------------------------------------
 
-class TestProp(Module, AutoCSR, ModuleDoc):
+class TestPropagation(Module, AutoCSR, ModuleDoc):
     """
     Propagation Test Module
 

modules/testRGB.py

@@ -24,12 +24,12 @@ class TestRgb(Module, AutoCSR, ModuleDoc):
 
         leds = Signal(3)
         self.comb += pads.eq(~leds)
-        self.specials += Instance("flipPwm",
+        self.specials += Instance("ledPwm",
             i_clk = ClockSignal(),
             i_rgb = self._out.storage,
             o_ledr = leds[0],
             o_ledg = leds[1],
             o_ledb = leds[2]
         )
-        platform.add_source("rtl/flipPwm.sv")
+        platform.add_source("rtl/ledPwm.sv")
 

rtl/dacAttenuation.sv

@@ -1,10 +1,10 @@
 `default_nettype none
 
-module dacVolume
+module dacAttenuation
 ( input  var       i_clk48   // Runs at 48MHz
 , input  var       i_rst48_n // Active low reset for sys_clk
 , input  var       i_valid   // Only update DAC volume when CSRStorage is written to
-, input  var [7:0] i_volume  // 8-bit volume control (0x00 = min, 0xFF = max)
+, input  var [7:0] i_atten   // 8-bit attenuation control (0x00 = min, 0xFF = max)
 , output var       o_sel_n   // DAC Control bus select (active low)
 , output var       o_clock   // DAC Control bus clock
 , output var       o_data    // DAC Control bus data (serial)
@@ -19,7 +19,7 @@ always_ff @(posedge i_clk48) // Capture when CSTStorage is written to
 logic [7:0] volume;
 always_ff @(posedge i_clk48) // Update volume setting when CSRStorage is written to
   if (!i_rst48_n)   volume <= 8'h00;
-  else if (i_valid) volume <= i_volume;
+  else if (i_valid) volume <= i_atten;
 
 logic [2:0] div_6m;
 always_ff @(posedge i_clk48) // Count 6MHz cycle

rtl/ledPwm.sv

@@ -1,6 +1,6 @@
 `default_nettype none
 
-module flipPwm
+module ledPwm
 ( input  var        clk
 , input  var [23:0] rgb
 , output var        ledr