StackSynth Final Year Project

Project Notes

• Guide on adding a new core (incomplete)
  • Using LiteEth on ECP5
  • Adding HW modules, lots more info in issue
    • Possible useful info in soc.py, Lines 1311 - 2106
• CORDIC Block Development Repository

Useful links

• FreeRTOS Quick Start Guide
  • Run FreeRTOS and multitasking on VexRiscv
  • Run FreeRTOS on VexRiscv and Measure/Tweak context switch overhead
  • kole-huang/picorvv32_soc - GitHub, possible base for FreeRTOS port on PicoRV32
• CAN Bus Implementation
  • CAN bus: Base Frame Format - Wikipedia
  • Texas Instruments: Introduction to CAN
  • Bosch CAN Specification 2.0
  • CAN Tx Frame Implementation using Verilog, reference for timing diagrams?
  • Datasheet for CAN Transceiver
  • Understanding Microchip’s CAN Module Bit Timing
• Sine Approximation for Sawtooth - Sine Conversion
  • Polynomial Approximation
    • Desmos Demonstration (Screenshot)
  • CORDIC Research
    • Area/Energy Efficient CORDIC Accelerator
    • Doulos SNUG Europe 2004 Paper, local copy of Verilog
    • ZIPcpu: Using a CORDIC to calculate sines and cosines in an FPGA
• API Reference migen, AsyncFIFO
• Guide on adding a new core (incomplete)
  • Using LiteEth on ECP5
  • Adding HW modules, lots more info in issue
    • Possible useful info in soc.py, Lines 1311 - 2106
    • Also generic_platform.py, Lines 324 - 522
  • Migen Guide
  • LiteX SPI Core
  • FoMu Example of using external Verilog
  • Automatic LiteX Documentation
• Migen (base for litex) GitHub Repository
• Litex Wiki: reusing SV or other cores
• Litex for Hardware Engineers
• Example of RTOS on LiteX
• Blog on using FreeRTOS on stock VexRiscV Core
• FreeRTOS on RiscV Blog Post
• Video on FreeRTOS on RiscV
• VexRiscV Source
• Summon FPGA Tools Repo
• Broken Flag issue when building litex
• On-board DAC Datasheet
• Definitely reference when talking about sending PCM data from the 48MHz RISC-V domain to the ~38MHz DAC domain
  • CDC Design Techniques - Sunburst Design
  • Async FIFO Design - Sunburst Design
  • Dual-Clock Async FIFO in SV - Verilog Pro
  • CDC Design 3 Part Series - Verilog Pro
  • Simple CDC - ZipCPU
  • CDC with an Async FIFO - ZipCPU
    • Source on GitHub - afifo.v
  • CDC with an FPGA - NandLand
    • Contained recommendations on signals, including using Almost-Empty/Full signals to avoid situations where the signal is invalid due to signal propegation & timing requirements
• LiteScope GitHub Repository - Scope to record signals internal to the FPGA Fabric
  • GitHub Wiki - Use LiteScope To Debug A SoC
  • litex-buildenv wiki on using LiteX
  • Posible irc discusions on LiteScope?

Cool Things To Note

• python -m litex.tools.litex_read_verilog ./rtl/flipPwm.sv allows for auto-gen of the LiteX Class needed to create an instance, however it does not set up the CSRStorage.
• Load Application Code To CPU
• Use LiteScope To Debug A SoC
• Use GDB with VexRiscv CPU
• Run Zephyr On Your SoC

Possible reference links

• OrangeCrab FPGA Product Page
• OrangeCrab FPGA Hardware Repo
• OrangeCrab FPGA Example Repo
  • Use both the Verilog and Blink examples, the CircuitPython example did not work due to the version of CircuitPython needed (I think?)
• OrangeCrab FPGA Store Listing
• OrangeCrab FPGA Github Docs
• Hackster post on OrangeCrab FPGA
• element14 post on OrangeCrab FPGA
• CNX Software post on OrangeCrab FPGA
• Example writeup of using OrangeCrab FPGA
• Amaranth / Migen Crash Course
• LiteX Soft-CPU, FPGA and Firmware Support
• FPGA MicroPython (FμPy)
• FuPy (FPGA MicroPython) on Mimas v2 and Arty
• enjoy-digital/litex GitHub
• litex/boot.c · enjoy-digital/litex
• litex/litex_setup.py · enjoy-digital/litex
• picolibc switch Issue #1045 · enjoy-digital/litex
• Vexriscv secure CPU Issue #1585 · enjoy-digital/litex
• LD_FLAGS Issue #825 · enjoy-digital/litex
• Home · enjoy-digital/litex Wiki
• gregdavill/linux-on-litex-vexriscv
• OrangeCrab-test-sw/hw
• gregdavill:orangecrab vs upstream · litex-hub/linux-on-litex-vexriscv
• Prebuilt Bitstreams and Linux/OpenSBI images for linux on litex
• linux-on-litex-vexriscv/buildroot/board
• litex-hub/litex-boards: LiteX boards files
• litex-boards/lattice_ecp5_evn.py
• litex-boards/lattice_ecp5_vip.py
• litex-boards/litex_boards/targets
• mwelling/orangecrab-test
• Use read_verilog in Yosys orangecrab example command
• litex example cannot find Yosys or nextpnr-ecp5 programs
• Migrate nMigen examples to Amaranth in orangecrab example
• RISC-V with custom gateware Issue #35 · orangecrab-fpga/orangecrab-hardware
• Lattice Diamond Compatibility Issue #41 · orangecrab-fpga/orangecrab-hardware
• timvideos/litex-buildenv
• Bare Metal · timvideos/litex-buildenv Wiki
• YosysHQ/nextpnr: nextpnr portable FPGA place and route tool
• Lattice FPGA SBCs can run Linux on RISC-V softcore
• litex_liteeth.c:undefined reference to `devm_platform_ioremap_resource_byname'
• Linux on LiteX-Vexriscv - Hacker News
• Running Zephyr RTOS on Mimas A7 using LiteX and RISC-V
• Downloads | OrangeCrab Docs
• Zephyr on Fomu FPGA
• Building a SoC with Litex. – controlpaths blog
• Running Linux on a Litex SoC. – controlpaths blog
• Say “Hello” to the OrangeCrab - Hackster.io
• LiteX Research Paper???
• learn-fpga/toolchain.md · BrunoLevy/learn-fpga
• Testing the OrangeCrab r0.1 Blog
• FOSS-for_FPGA Slideshow
• FPGA Tooling on Ubuntu 20.04 - FPGA Dev
• Reddit question on riscv core on fpga
• linux-on-litex-vexriscv/orangecrab_with_enc28j60_on_spi.md
• Previous paper using LiteX