From 2829a32dc673b5f6f4b5656eb787969dedb17108 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Sun, 18 Jun 2023 17:22:08 +0100 Subject: [PATCH] Tidy project Rename modules for clarity Move LiteX modules into `modules/` Move extras into `notes/` --- .gitignore | 2 +- make.py | 31 ++++++++---------- testCAN.py => modules/canReceiver.py | 0 dacVolume.py => modules/dacAttenuation.py | 14 ++++---- testWave.py => modules/genWave.py | 7 ++-- testProp.py => modules/testPropagation.py | 2 +- testRGB.py => modules/testRGB.py | 4 +-- testSaw.py => modules/testSaw.py | 0 .../sine_poly_approx.png | Bin .../testPropTiming.vcd | 0 rtl/{dacVolume.sv => dacAttenuation.sv} | 6 ++-- rtl/{flipPwm.sv => ledPwm.sv} | 2 +- 12 files changed, 31 insertions(+), 37 deletions(-) rename testCAN.py => modules/canReceiver.py (100%) rename dacVolume.py => modules/dacAttenuation.py (70%) rename testWave.py => modules/genWave.py (94%) rename testProp.py => modules/testPropagation.py (95%) rename testRGB.py => modules/testRGB.py (92%) rename testSaw.py => modules/testSaw.py (100%) rename sine_poly_approx.png => notes/sine_poly_approx.png (100%) rename testPropTiming.vcd => notes/testPropTiming.vcd (100%) rename rtl/{dacVolume.sv => dacAttenuation.sv} (91%) rename rtl/{flipPwm.sv => ledPwm.sv} (96%) diff --git a/.gitignore b/.gitignore index f712587..0db241b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,7 +1,7 @@ /.vscode/ /build/ /docs/ -/__pycache__/ +__pycache__/ /demo/*.o /demo/*.d /demo/demo.bin diff --git a/make.py b/make.py index 6eafff8..c29c000 100755 --- a/make.py +++ b/make.py @@ -194,7 +194,7 @@ class BaseSoC(SoCCore): # pads = platform.request_all("user_led"), # sys_clk_freq = sys_clk_freq # ) - from testRGB import TestRgb + from modules.testRGB import TestRgb self.leds = TestRgb( platform = platform, pads = platform.request_all("user_led") @@ -228,7 +228,7 @@ class BaseSoC(SoCCore): ]) # CAN Receiver Block ----------------------------------------------------------------------- - from testCAN import CanReceiver + from modules.canReceiver import CanReceiver self.can = CanReceiver( platform = platform, pads = platform.request("can") @@ -236,25 +236,20 @@ class BaseSoC(SoCCore): self.irq.add("can", use_loc_if_exists=True) # DAC Control / Audio Blocks --------------------------------------------------------------- - from testWave import TestWave - self.audio = TestWave( + from modules.genWave import GenerateWave + self.audio = GenerateWave( platform = platform, pads = platform.request("dac_pcm") ) - # from testSaw import TestSaw - # self.audio = TestSaw( - # platform = platform, - # pads = platform.request("dac_pcm") - # ) - # from dacVolume import DacVolume - # self.dac_vol = DacVolume( + # from modules.dacAttenuation import DacAttenuation + # self.dac_atten = DacAttenuation( # platform = platform, # pads = platform.request("dac_ctrl") # ) # Propagation Delay Test ------------------------------------------------------------------- - # from testProp import TestProp - # self.proptest = TestProp(platform = platform) + # from modules.testPropagation import TestPropagation + # self.proptest = TestPropagation(platform = platform) # LiteScope Analyzer ----------------------------------------------------------------------- self.add_uartbone(name="debug_uart", baudrate=921600) @@ -264,11 +259,11 @@ class BaseSoC(SoCCore): # self.proptest.o_sin, self.can.can_rx, self.can.can_tx, - # self.dac_vol.volume.re, - # self.dac_vol.volume.storage, - # self.dac_vol.m_sel_n, - # self.dac_vol.m_clock, - # self.dac_vol.m_data, + # self.dac_atten.atten.re, + # self.dac_atten.atten.storage, + # self.dac_atten.m_sel_n, + # self.dac_atten.m_clock, + # self.dac_atten.m_data, self.audio.osc.re, # self.audio.osc.storage, self.audio.tf.re, diff --git a/testCAN.py b/modules/canReceiver.py similarity index 100% rename from testCAN.py rename to modules/canReceiver.py diff --git a/dacVolume.py b/modules/dacAttenuation.py similarity index 70% rename from dacVolume.py rename to modules/dacAttenuation.py index 01167fb..f8e7ae0 100644 --- a/dacVolume.py +++ b/modules/dacAttenuation.py @@ -5,17 +5,17 @@ from litex.soc.integration.doc import ModuleDoc # Test RGB Module ---------------------------------------------------------------------------------- -class DacVolume(Module, AutoCSR, ModuleDoc): +class DacAttenuation(Module, AutoCSR, ModuleDoc): """ - DAC Volume Control Module + DAC Attenuation Control Module Set the Attenuation of the PCM1780 DAC """ def __init__(self, platform, pads): - platform.add_source("rtl/dacVolume.sv") + platform.add_source("rtl/dacAttenuation.sv") self.pads = pads - self.volume = CSRStorage(size = 8, reset = 128, description = "PCM1780: Attenuation Control") + self.atten = CSRStorage(size = 8, reset = 128, description = "PCM1780: Attenuation Control") self.m_sel_n = Signal() self.m_clock = Signal() @@ -23,11 +23,11 @@ class DacVolume(Module, AutoCSR, ModuleDoc): # # # - self.specials += Instance("dacVolume", + self.specials += Instance("dacAttenuation", i_i_clk48 = ClockSignal(), i_i_rst48_n = ~ResetSignal(), - i_i_valid = self.volume.re, - i_i_volume = self.volume.storage, + i_i_valid = self.atten.re, + i_i_atten = self.atten.storage, o_o_sel_n = self.m_sel_n, o_o_clock = self.m_clock, o_o_data = self.m_data, diff --git a/testWave.py b/modules/genWave.py similarity index 94% rename from testWave.py rename to modules/genWave.py index eccc762..221c055 100644 --- a/testWave.py +++ b/modules/genWave.py @@ -4,13 +4,12 @@ from litex.soc.interconnect.csr import * from migen.genlib.fifo import AsyncFIFO as MigenAsyncFIFO from litex.soc.integration.doc import ModuleDoc -# Test RGB Module ---------------------------------------------------------------------------------- - -class TestWave(Module, AutoCSR, ModuleDoc): +class GenerateWave(Module, AutoCSR, ModuleDoc): """ - Multi Wave Test Module + Multi Wave Generation Module Set the target frequency and waveform outpput for each of 128 oscillators. + Outputs samples normalised in range 0.5-1x max amplitude. """ def __init__(self, platform, pads): platform.add_source("rtl/cordic.sv") diff --git a/testProp.py b/modules/testPropagation.py similarity index 95% rename from testProp.py rename to modules/testPropagation.py index 7eddcb9..d75c7af 100644 --- a/testProp.py +++ b/modules/testPropagation.py @@ -5,7 +5,7 @@ from litex.soc.integration.doc import ModuleDoc # Test RGB Module ---------------------------------------------------------------------------------- -class TestProp(Module, AutoCSR, ModuleDoc): +class TestPropagation(Module, AutoCSR, ModuleDoc): """ Propagation Test Module diff --git a/testRGB.py b/modules/testRGB.py similarity index 92% rename from testRGB.py rename to modules/testRGB.py index 8ae91fc..7466b47 100644 --- a/testRGB.py +++ b/modules/testRGB.py @@ -24,12 +24,12 @@ class TestRgb(Module, AutoCSR, ModuleDoc): leds = Signal(3) self.comb += pads.eq(~leds) - self.specials += Instance("flipPwm", + self.specials += Instance("ledPwm", i_clk = ClockSignal(), i_rgb = self._out.storage, o_ledr = leds[0], o_ledg = leds[1], o_ledb = leds[2] ) - platform.add_source("rtl/flipPwm.sv") + platform.add_source("rtl/ledPwm.sv") diff --git a/testSaw.py b/modules/testSaw.py similarity index 100% rename from testSaw.py rename to modules/testSaw.py diff --git a/sine_poly_approx.png b/notes/sine_poly_approx.png similarity index 100% rename from sine_poly_approx.png rename to notes/sine_poly_approx.png diff --git a/testPropTiming.vcd b/notes/testPropTiming.vcd similarity index 100% rename from testPropTiming.vcd rename to notes/testPropTiming.vcd diff --git a/rtl/dacVolume.sv b/rtl/dacAttenuation.sv similarity index 91% rename from rtl/dacVolume.sv rename to rtl/dacAttenuation.sv index e1243d7..086008d 100644 --- a/rtl/dacVolume.sv +++ b/rtl/dacAttenuation.sv @@ -1,10 +1,10 @@ `default_nettype none -module dacVolume +module dacAttenuation ( input var i_clk48 // Runs at 48MHz , input var i_rst48_n // Active low reset for sys_clk , input var i_valid // Only update DAC volume when CSRStorage is written to -, input var [7:0] i_volume // 8-bit volume control (0x00 = min, 0xFF = max) +, input var [7:0] i_atten // 8-bit attenuation control (0x00 = min, 0xFF = max) , output var o_sel_n // DAC Control bus select (active low) , output var o_clock // DAC Control bus clock , output var o_data // DAC Control bus data (serial) @@ -19,7 +19,7 @@ always_ff @(posedge i_clk48) // Capture when CSTStorage is written to logic [7:0] volume; always_ff @(posedge i_clk48) // Update volume setting when CSRStorage is written to if (!i_rst48_n) volume <= 8'h00; - else if (i_valid) volume <= i_volume; + else if (i_valid) volume <= i_atten; logic [2:0] div_6m; always_ff @(posedge i_clk48) // Count 6MHz cycle diff --git a/rtl/flipPwm.sv b/rtl/ledPwm.sv similarity index 96% rename from rtl/flipPwm.sv rename to rtl/ledPwm.sv index 30a7034..1110168 100644 --- a/rtl/flipPwm.sv +++ b/rtl/ledPwm.sv @@ -1,6 +1,6 @@ `default_nettype none -module flipPwm +module ledPwm ( input var clk , input var [23:0] rgb , output var ledr