Commit graph

16 commits

Author SHA1 Message Date
Aadi Desai cc0ab0f2b4
Add useful links on gdb and zephyr 2023-03-04 14:54:57 +00:00
Aadi Desai f5b923ca57
Add DAC Pin definitions to platform in make.py 2023-03-04 14:54:36 +00:00
Aadi Desai 8c0eee54b4
Remove reset value from TestRgb 2023-03-04 14:54:09 +00:00
Aadi Desai 5de7bc535a
Update make.py with GPIO pads and TestRgb module using custom clock 2023-03-03 17:07:19 +00:00
Aadi Desai 07f57f4cf8
Add LiteX Module for TestRgb inc module docs 2023-03-03 17:06:20 +00:00
Aadi Desai 52eb0bdaf7
Signal prefixes are removed by migen, so double 2023-03-03 17:05:53 +00:00
Aadi Desai 740316a47f
Add LiteX Docs link to readme 2023-03-03 17:05:22 +00:00
Aadi Desai 529efcaf9f
Add pwm module to set LED colour from LiteX Console 2023-03-03 17:05:00 +00:00
Aadi Desai d960053a7e
Update flip.sv to cycle across colours using 48MHz 2023-03-03 17:04:22 +00:00
Aadi Desai 81b2d004a5
Update build script
Exit on error
Build documentation & move to project root
Move built bitstream to Win11 Desktop
2023-03-03 17:03:43 +00:00
Aadi Desai b90a0efadc
Add more useful links to readme backup 2023-02-26 19:42:08 +00:00
Aadi Desai 2e83f912d1
Update make Python script to use test LiteX Module 2023-02-26 19:41:51 +00:00
Aadi Desai 3ea0c58728
Add build shortcut script 2023-02-26 19:41:10 +00:00
Aadi Desai e1b0d5c28c
Add testing SystemVerilog and LiteX Module 2023-02-26 19:40:56 +00:00
Aadi Desai 9322fe0fd4
Add readme notes 2023-02-26 14:59:50 +00:00
Aadi Desai 6d8c1059fa
Initial commit to prevent data loss
such as in the case of sudden laptop death
2023-02-05 00:56:34 +00:00