Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London
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2023-02-26 19:42:08 +00:00
rtl Add testing SystemVerilog and LiteX Module 2023-02-26 19:40:56 +00:00
.gitignore Add build shortcut script 2023-02-26 19:41:10 +00:00
build.sh Add build shortcut script 2023-02-26 19:41:10 +00:00
make.py Update make Python script to use test LiteX Module 2023-02-26 19:41:51 +00:00
options.sh Initial commit to prevent data loss 2023-02-05 00:56:34 +00:00
readme.md Add more useful links to readme backup 2023-02-26 19:42:08 +00:00
testLED.py Add testing SystemVerilog and LiteX Module 2023-02-26 19:40:56 +00:00

StackSynth Final Year Project

Project Notes