supleed2/EIE4-FYP
1
0
Fork 0
mirror of https://github.com/supleed2/EIE4-FYP.git synced 2024-09-19 21:36:17 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add more useful links to readme backup

Browse source
This commit is contained in:
Aadi Desai 2023-02-26 19:42:08 +00:00
parent 2e83f912d1
commit b90a0efadc
No known key found for this signature in database
1 changed files with 5 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
readme.md
View file

@ -2,14 +2,16 @@
## Project Notes
### Useful links
- [Guide on adding a new core (incomplete)](https://github.com/enjoy-digital/litex/wiki/Add-A-New-Core)
- [Using LiteEth on ECP5](https://github.com/enjoy-digital/liteeth/issues/66)
- [Adding HW modules](https://github.com/enjoy-digital/litex/issues/746), lots more info in issue
- Possible useful info in [soc.py](litex/litex/soc/integration/soc.py), Lines 1311 - 2106
- Also [generic_platform.py](litex/litex/build/generic_platform.py), Lines 324 - 522
### Useful links
- [Migen Guide](https://m-labs.hk/migen/manual/fhdl.html)
- [LiteX SPI Core](https://github.com/litex-hub/litespi)
- [FoMu Example of using external Verilog](https://github.com/im-tomu/foboot/blob/c7ee25b3d10dba0c1df67e793c4e2585577e7a39/hw/foboot-bitstream.py#L507-L537)
- [Migen (base for litex) GitHub Repository](https://github.com/m-labs/migen)
- [Litex Wiki: reusing SV or other cores](https://github.com/enjoy-digital/litex/wiki/Reuse-a-(System)Verilog,-VHDL,-(n)Migen,-Spinal-HDL,-Chisel-core)
- [Litex for Hardware Engineers](https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers)