From b90a0efadc669bbd996c9dad5cc3e5c22628e12c Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Sun, 26 Feb 2023 19:42:08 +0000
Subject: [PATCH] Add more useful links to readme backup

---
 readme.md | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/readme.md b/readme.md
index febfda3..dcfbcea 100644
--- a/readme.md
+++ b/readme.md
@@ -2,14 +2,16 @@
 
 ## Project Notes
 
+### Useful links
+
 - [Guide on adding a new core (incomplete)](https://github.com/enjoy-digital/litex/wiki/Add-A-New-Core)
   - [Using LiteEth on ECP5](https://github.com/enjoy-digital/liteeth/issues/66)
   - [Adding HW modules](https://github.com/enjoy-digital/litex/issues/746), lots more info in issue
     - Possible useful info in [soc.py](litex/litex/soc/integration/soc.py), Lines 1311 - 2106
     - Also [generic_platform.py](litex/litex/build/generic_platform.py), Lines 324 - 522
-
-### Useful links
-
+  - [Migen Guide](https://m-labs.hk/migen/manual/fhdl.html)
+  - [LiteX SPI Core](https://github.com/litex-hub/litespi)
+  - [FoMu Example of using external Verilog](https://github.com/im-tomu/foboot/blob/c7ee25b3d10dba0c1df67e793c4e2585577e7a39/hw/foboot-bitstream.py#L507-L537)
 - [Migen (base for litex) GitHub Repository](https://github.com/m-labs/migen)
 - [Litex Wiki: reusing SV or other cores](https://github.com/enjoy-digital/litex/wiki/Reuse-a-(System)Verilog,-VHDL,-(n)Migen,-Spinal-HDL,-Chisel-core)
 - [Litex for Hardware Engineers](https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers)