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audio-synthesiscan-buscordicecp5embedded-systemslitexorangecrabrisc-vstacksynthsystemverilogvexriscvwaveform-generator
Aadi Desai
81b2d004a5
Exit on error Build documentation & move to project root Move built bitstream to Win11 Desktop |
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| build.sh | ||
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| options.sh | ||
| readme.md | ||
| testLED.py | ||
StackSynth Final Year Project
Project Notes
Useful links
- Guide on adding a new core (incomplete)
- Using LiteEth on ECP5
- Adding HW modules, lots more info in issue
- Possible useful info in soc.py, Lines 1311 - 2106
- Also generic_platform.py, Lines 324 - 522
- Migen Guide
- LiteX SPI Core
- FoMu Example of using external Verilog
- Migen (base for litex) GitHub Repository
- Litex Wiki: reusing SV or other cores
- Litex for Hardware Engineers
- Example of RTOS on LiteX
- Blog on using FreeRTOS on stock VexRiscV Core
- FreeRTOS on RiscV Blog Post
- Video on FreeRTOS on RiscV
- VexRiscV Source
- Summon FPGA Tools Repo
- Broken Flag issue when building litex
- On-board DAC Datasheet
Possible reference links
- OrangeCrab FPGA Product Page
- OrangeCrab FPGA Hardware Repo
- OrangeCrab FPGA Example Repo
- Use both the Verilog and Blink examples, the CircuitPython example did not work due to the version of CircuitPython needed (I think?)
- OrangeCrab FPGA Store Listing
- OrangeCrab FPGA Github Docs
- Hackster post on OrangeCrab FPGA
- element14 post on OrangeCrab FPGA
- CNX Software post on OrangeCrab FPGA
- Example writeup of using OrangeCrab FPGA
- Amaranth / Migen Crash Course
- LiteX Soft-CPU, FPGA and Firmware Support
- FPGA MicroPython (FμPy)
- FuPy (FPGA MicroPython) on Mimas v2 and Arty
- enjoy-digital/litex GitHub
- litex/boot.c · enjoy-digital/litex
- litex/litex_setup.py · enjoy-digital/litex
- picolibc switch Issue #1045 · enjoy-digital/litex
- Vexriscv secure CPU Issue #1585 · enjoy-digital/litex
- LD_FLAGS Issue #825 · enjoy-digital/litex
- Home · enjoy-digital/litex Wiki
- gregdavill/linux-on-litex-vexriscv
- OrangeCrab-test-sw/hw
- gregdavill:orangecrab vs upstream · litex-hub/linux-on-litex-vexriscv
- Prebuilt Bitstreams and Linux/OpenSBI images for linux on litex
- linux-on-litex-vexriscv/buildroot/board
- litex-hub/litex-boards: LiteX boards files
- litex-boards/lattice_ecp5_evn.py
- litex-boards/lattice_ecp5_vip.py
- litex-boards/litex_boards/targets
- mwelling/orangecrab-test
- Use read_verilog in Yosys orangecrab example command
- litex example cannot find Yosys or nextpnr-ecp5 programs
- Migrate nMigen examples to Amaranth in orangecrab example
- RISC-V with custom gateware Issue #35 · orangecrab-fpga/orangecrab-hardware
- Lattice Diamond Compatibility Issue #41 · orangecrab-fpga/orangecrab-hardware
- timvideos/litex-buildenv
- Bare Metal · timvideos/litex-buildenv Wiki
- YosysHQ/nextpnr: nextpnr portable FPGA place and route tool
- Lattice FPGA SBCs can run Linux on RISC-V softcore
- litex_liteeth.c:undefined reference to `devm_platform_ioremap_resource_byname'
- Linux on LiteX-Vexriscv - Hacker News
- Running Zephyr RTOS on Mimas A7 using LiteX and RISC-V
- Downloads | OrangeCrab Docs
- Zephyr on Fomu FPGA
- Building a SoC with Litex. – controlpaths blog
- Running Linux on a Litex SoC. – controlpaths blog
- Say “Hello” to the OrangeCrab - Hackster.io
- LiteX Research Paper???
- learn-fpga/toolchain.md · BrunoLevy/learn-fpga
- Testing the OrangeCrab r0.1 Blog
- FOSS-for_FPGA Slideshow
- FPGA Tooling on Ubuntu 20.04 - FPGA Dev
- Reddit question on riscv core on fpga
- linux-on-litex-vexriscv/orangecrab_with_enc28j60_on_spi.md