supleed2/ELEC70056-HSV-CW2
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6 commits

Author SHA1 Message Date
Alden0012 4edfce0e03 Add initial assume to AHBGPIO.sv 2022-11-08 17:27:39 +00:00
Alden0012 0f8578e1b8 Add assertions to AHBGPIO.sv 2022-11-08 17:04:59 +00:00
Aadi Desai 0d4099ce15 Update AHBVGASYS.sv to SystemVerilog and style 2022-11-07 13:57:19 +00:00
Aadi Desai 018013d3c8 Add parity generation and checking to AHBGPIO.sv 2022-11-07 13:36:56 +00:00
Aadi Desai c83b8a73f1 Switch all Verilog files to SystemVerilog file endings 2022-11-07 12:58:43 +00:00
Aadi Desai dcdda4d9e1 Initial Commit 2022-11-07 12:41:05 +00:00