Add specific entries to .gitignore

For Verilog and C source files within project
This commit is contained in:
Aadi Desai 2022-01-30 17:17:51 +00:00
parent dc28e5c175
commit 94e215043a
No known key found for this signature in database
GPG key ID: CFFFE425830EF4D9

5
.gitignore vendored
View file

@ -1,6 +1,11 @@
** **
!system_template_de1_soc/
!*.v !*.v
!*.qsys !*.qsys
!system_template_de1_soc/software/
!system_template_de1_soc/software/*
system_template_de1_soc/software/*_bsp
!system_template_de1_soc/software/*/*.c
!DSD_coursework_DE1-SoC.pdf !DSD_coursework_DE1-SoC.pdf
!README.md !README.md
!Python/ !Python/