supleed2/ELEC50010-IAC-CW
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48 commits 2 branches 0 tags 9.2 MiB
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5 commits

Author SHA1 Message Date
Aadi Desai d347475b64 Update mips_cpu_regfile.v 
lb, lbu, lh, lhu now  select data according to address alignment
$0 is assigned to 0, may cause an error when written to, unknown.
 2020-12-06 17:42:23 +00:00
jl7719 c5167645e7 Fix overall w.r.t iverilog compiler error 2020-12-06 15:44:58 +09:00
Aadi Desai 847bf92add Fix regfile hazard from storing when inputs change 2020-12-02 19:13:41 +00:00
Aadi Desai 27cccc28b8 Added partial loads to regfile 
Partial reads are handled within the ALU
 2020-12-02 01:04:57 +00:00
Aadi Desai 3433337eba Added Regfile 
Missing partial/misaligned loads
 2020-12-01 23:04:43 +00:00