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35 lines
1.1 KiB
Verilog
35 lines
1.1 KiB
Verilog
module regfile(
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input logic clk, //clock input for triggering write port
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input logic[4:0] readreg1, //read port 1 selector
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input logic[4:0] readreg2, //read port 2 selector
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input logic[4:0] writereg, //write port selector
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input logic[31:0] writedata, //write port input data
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input logic regwrite, //enable line for write port
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output logic[31:0] readdata1, //read port 1 output
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output logic[31:0] readdata2, //read port 2 output
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output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
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);
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reg[31:0] memory [31:0]; //32 register slots, 32-bits wide
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initial begin
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integer i; //Initialise to zero by default
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for (i = 0; i < 31; i++) begin
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memory[i] = 0;
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end
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end
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assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
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always_comb begin
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readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector
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readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
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end
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always_ff @(posedge clk) begin
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if (regwrite) begin
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memory[writereg] <= writedata;
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end
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end
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endmodule : regfile |