Commit graph

28 commits

Author SHA1 Message Date
Aadi Desai 6c0554538c Rename .v to .sv for Quartus to detect as SystemVerilog 2020-12-19 08:43:20 -08:00
Aadi Desai 76fbc7d5c4 Remove enum from control.v using find&replace
This should be functionally identical
2020-12-19 15:40:29 +00:00
Aadi Desai e513096ed8 Add missing opcodes to CtrlMemRead = 0 2020-12-17 09:43:47 -08:00
Aadi Desai ad394c7d7d Adding missing opcodes to CtrlMemRead 2020-12-17 09:02:58 -08:00
Aadi Desai cb29efd034 Merge branch 'main' into bus_wrapper 2020-12-17 16:46:01 +00:00
Aadi Desai 2be1978a36 Add initial value to npc, add JR to CtrlMemRead 2020-12-17 08:43:58 -08:00
jl7719 cfebb403ba Delete from source files and the testbench 2020-12-17 15:02:59 +00:00
jl7719 2d9cca262d Fix display appearing at the end of log file 2020-12-17 14:51:08 +00:00
Jeevaha Coelho 7185f7e7e6 Fixed BGEZAL 2020-12-16 07:00:46 -08:00
Jeevaha Coelho 2673e23137 FIxed PC! 2020-12-16 05:21:57 -08:00
jl7719 ad68ab0974 Debugging and debugging
PC, Jump instr, branches
2020-12-16 12:29:22 +00:00
jl7719 0891f7e653 Debug mult/div to work
it works now
2020-12-16 08:38:46 +00:00
jl7719 4ff160db1a Fix syntax errors from mult/div 2020-12-16 05:04:45 +00:00
Jeevaha Coelho 90917f7566 Updated PC, Harv, ALU, to work w/ MULT(U), DIV(U) 2020-12-15 13:48:28 -08:00
jl7719 51dbe68ea8 Fix running on different environment issue
Now completely shifted to Ubuntu 18.04 setup should work for everyone
2020-12-14 17:38:39 +00:00
jl7719 943745a1e0 Tested all that can be tested for now
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
2020-12-13 14:40:16 +09:00
jl7719 c31344c55f More testcases, testing, debugging 2020-12-13 01:25:36 +09:00
jl7719 3594365a25 Create branch jl7719
Can test for normal pc incrementing instr
2020-12-11 19:45:13 +09:00
jl7719 04b1ed4fed Update control and memory
Fixed some errors when testing
2020-12-10 22:27:08 +09:00
jc4419 3a2fde81b2 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-09 16:27:20 +04:00
jc4419 4b8a56ee2f Fixed if logic for control 2020-12-09 16:24:21 +04:00
jl7719 c5aed43ab4 Update to test each instruction with a small memory 2020-12-09 16:47:58 +09:00
jc4419 9de2b59bbb Updated Harvard, ALU, PC, Control, and Regfile 2020-12-08 01:46:01 +04:00
jc4419 8f5e582f33 Updated ALU - Minor Syntax Fixes 2020-12-07 18:18:19 +04:00
jc4419 9198c4f51b Updated ALU and Control 2020-12-07 15:49:44 +04:00
yhp19 d1d64ae747 changed control for aluop and naming 2020-12-02 21:55:17 +08:00
yhp19 63b017d552 added control comments 2020-12-02 15:43:30 +08:00
yhp19 4edcb07e1f added control 2020-12-01 15:30:57 +08:00