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https://github.com/supleed2/ELEC50010-IAC-CW.git
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202 lines
7.7 KiB
Verilog
202 lines
7.7 KiB
Verilog
module mips_cpu_control(
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input logic[31:0] Instr,
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input logic ALUCond,
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output logic CtrlRegDst,
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output logic[1:0] CtrlPC,
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output logic CtrlMemRead,
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output logic CtrlMemtoReg,
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output logic[4:0] CtrlALUOp,
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output logic[4:0] Ctrlshamt,
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output logic CtrlMemWrite,
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output logic CtrlALUSrc,
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output logic CtrlRegWrite
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);
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/* logic[5:0] op;
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logic[5:0] funct;
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logic[4:0] rt; */
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/* assign op = Instr[31:26];
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assign funct = Instr[5:0];
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assign rt = Instr[20:16]; */
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typedef enum logic[5:0]{
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SPECIAL = 6'd0,
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REGIMM = 6'd1,
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J = 6'd2,
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JAL = 6'd3,
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BEQ = 6'd4,
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BNE = 6'd5,
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BLEZ = 6'd6,
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BGTZ = 6'd7,
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ADDI = 6'd8,
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ADDIU = 6'd9,
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SLTI = 6'd10,
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SLTIU = 6'd11,
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ANDI = 6'd12,
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ORI = 6'd13,
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XORI = 6'd14,
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LUI = 6'd15,
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LB = 6'd32,
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LH = 6'd33,
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LWL = 6'd34,
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LW = 6'd35,
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LBU = 6'd36,
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LHU = 6'd37,
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LWR = 6'd38,
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SB = 6'd40,
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SH = 6'd41,
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SW = 6'd43
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} op_enum;
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op_enum op;
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assign op = Instr[31:26];
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typedef enum logic[5:0]{
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SLL = 6'd0,
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SRL = 6'd2,
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SRA = 6'd3,
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SLLV = 6'd4,
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SRLV = 6'd6,
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SRAV = 6'd7,
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JR = 6'd8,
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JALR = 6'd9,
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MTHI = 6'd17,
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MTLO = 6'd19,
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MULT = 6'd24,
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MULTU = 6'd25,
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DIV = 6'd26,
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DIVU = 6'd27,
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ADDU = 6'd33,
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SUBU = 6'd35,
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AND = 6'd36,
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OR = 6'd37,
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XOR = 6'd38,
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SLT = 6'd42,
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SLTU = 6'd43
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} funct_enum;
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funct_enum funct;
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assign funct = Instr[5:0];
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typedef enum logic[4:0]{
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BLTZ = 5'd0,
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BGEZ = 5'd1,
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BLTZAL = 5'd16,
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BGEZAL = 5'd17
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} rt_enum;
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rt_enum rt;
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assign rt = Instr[20:16];
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always_comb begin
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//CtrlRegDst logic
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if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI))begin
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CtrlRegDst = 0; //Write address comes from rt
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end else if (op == (SPECIAL & (funct == (ADDU | AND | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR))))begin
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CtrlRegDst = 1; //Write address comes from rd
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end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlPC logic
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if(op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL)))))begin
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CtrlPC = 2'd1; // Branches - Jumps relative to PC
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end else if(op == (J | JAL))begin
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CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
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end else if(op == (JR | JALR))begin
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CtrlPC = 2'd3; // Jumps using Register.
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end else begin CtrlPC = 2'd0;end // No jumps, just increment to next word
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//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
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if(op == (LB | LBU | LH | LHU | LW | LWL | LWR))begin
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CtrlMemRead = 1;//Memory is read enabled
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CtrlMemtoReg = 1;//write data port of memory is fed from data memory
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end else if (op == (ADDIU | ANDI | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MTHI | MTLO | MULT | MULTU | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
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CtrlMemRead = 0;//Memory is read disabled
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CtrlMemtoReg = 0;//write data port of memory if fed from ALURes
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end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlALUOp Logic
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if(op == (ADDIU | (SPECIAL & (funct == ADDU))))begin
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CtrlALUOp = 5'd0; //ADD from ALUOps
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end else if (op == (ANDI | (SPECIAL & (funct == AND))))begin
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CtrlALUOp = 5'd4;//AND from ALUOps
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end else if (op == BEQ) begin
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CtrlALUOp = 5'd13;//EQ from ALUOps
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end else if (op == (REGIMM & (rt == (BGEZ | BGEZAL))))begin
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CtrlALUOp = 5'd17;//GEQ from ALUOps
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end else if (op == BGTZ)begin
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CtrlALUOp = 5'd16;//GRT from ALUOps
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end else if (op == BLEZ)begin
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CtrlALUOp = 5'd15;//LEQ from ALUOps
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end else if (op == (REGIMM & (rt == (BLTZ | BLTZAL))))begin
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CtrlALUOp = 5'd14;//LES from ALUOps
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end else if (OP == BNE)begin
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CtrlALUOp = 5'd18;//NEQ from ALUOps
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end else if (op == (SPECIAL & (funct == DIV)))begin
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CtrlALUOp = 5'd3;//DIV from ALUOps
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end else if (op == (SPECIAL & (funct == DIVU)))begin
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CtrlALUOp = 5'd23;//DIVU from ALUOps
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end else if (op == (LB | LBU | LH | LHU | LW | LWL | LWR | SB | SBH | SW))begin
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CtrlALUOp = 5'd0;//ADD from ALUOps
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end else if (op == LUI)begin
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CtrlALUOp = 5'd7;//SLL from ALUOps
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end else if (op == (SPECIAL & (funct == MTHI | MTLO)))begin
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CtrlALUOp = 5'd19;//PAS from ALUOps
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end else if (op == (SPECIAL & (funct == MULT)))begin
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CtrlALUOp = 5'd2;//MUL from ALUOps
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end else if (op == (SPECIAL & (funct == MULTU)))begin
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CtrlALUOp = 5'd22;//MULU from ALUOps
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end else if (op == (ORI | (SPECIAL & (funct == OR))))begin
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CtrlALUOp = 5'd5;//OR from ALUOps
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end else if (op == (SPECIAL & (funct == SLL)))begin
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CtrlALUOp = 5'd7;//SLL from ALUOps
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end else if (op == (SPECIAL & (funct == SLLV)))begin
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CtrlALUOp = 5'd8;//SLLV from ALUOps
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end else if (op == (SPECIAL & (funct == SRA)))begin
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CtrlALUOp = 5'd11;//SRA from ALUOps
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end else if (op == (SPECIAL & (funct == SRAV)))begin
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CtrlALUOp = 5'd12;//SRAV from ALUOps
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end else if (op == (SPECIAL & (funct == SRL)))begin
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CtrlALUOp = 5'd9;//SRL from ALUOps
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end else if (op == (SPECIAL & (funct == SRLV)))begin
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CtrlALUOp = 5'd10;//SRLV from ALUOps
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end else if (op == (SLTI | (SPECIAL & (funct == SLT))))begin
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CtrlALUOp = 5'd20;//SLT from ALUOps
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end else if (op == (SLTIU | (SPECIAL & (funct == SLTU))))begin
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CtrlALUOp = 5'd21;//SLTU from ALUOps
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end else if (op == (SPECIAL & (funct == SUBU)))begin
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CtrlALUOp = 5'd1;//SUB from ALUOps
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end else if (op == (XORI | (SPECIAL & (funct == XOR))))begin
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CtrlALUOp = 5'd6;//XOR from ALUOps
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end else begin
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CtrlALUOp = 5'bxxxxx;
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end
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//Ctrlshamt logic
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if(op == (SPECIAL & (funct == (SRA | SRL | SLL))))begin
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Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
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end else if(op == LUI)begin
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Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
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end else begin Ctrlshamt = 5'bxxxxx;end
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//CtrlMemWrite logic
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if(op == (SB | SH | SW))begin
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CtrlMemWrite = 1;//Memory is write enabled
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end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
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//CtrlALUSrc logic
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if(op == (ADDIU | ANDI | LUI | ORI | SLTI | SLTIU | XORI | LB | LBU | LH | LHU | LW | LWL | LWR | SB | SH | SW))begin
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CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
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end else if (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL))) | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | OR | SLLV | SLT | SLTU | SRAV | SRLV | SUBU | XOR)))))begin
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CtrlALUSrc = 0;///ALU Bus B is fed from rt.
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end else begin CtrlALUSrc = 1'bx;end
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//CtrlRegWrite logic
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if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
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CtrlRegWrite = 1;//The Registers are Write Enabled
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end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
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end
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endmodule
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