12 commits

Author	SHA1	Message	Date
Aadi Desai	a598321539	Use base+offset[1:0] for partial loads instead of base[1:0]	2020-12-19 10:22:44 +00:00
jl7719	cfebb403ba	Delete from source files and the testbench	2020-12-17 15:02:59 +00:00
jl7719	0891f7e653	Debug mult/div to work ... it works now	2020-12-16 08:38:46 +00:00
jl7719	943745a1e0	Tested all that can be tested for now ... Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus	2020-12-13 14:40:16 +09:00
jl7719	c31344c55f	More testcases, testing, debugging	2020-12-13 01:25:36 +09:00
Aadi Desai	6becea322f	Update mips_cpu_regfile.v ... Regfile should now compile, write is skipped if $0 is the destination register	2020-12-08 13:23:08 +00:00
jc4419	9de2b59bbb	Updated Harvard, ALU, PC, Control, and Regfile	2020-12-08 01:46:01 +04:00
Aadi Desai	d347475b64	Update mips_cpu_regfile.v ... lb, lbu, lh, lhu now select data according to address alignment $0 is assigned to 0, may cause an error when written to, unknown.	2020-12-06 17:42:23 +00:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
Aadi Desai	847bf92add	Fix regfile hazard from storing when inputs change	2020-12-02 19:13:41 +00:00
Aadi Desai	27cccc28b8	Added partial loads to regfile ... Partial reads are handled within the ALU	2020-12-02 01:04:57 +00:00
Aadi Desai	3433337eba	Added Regfile ... Missing partial/misaligned loads	2020-12-01 23:04:43 +00:00