supleed2/ELEC50010-IAC-CW
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49 commits

Author SHA1 Message Date
jl7719 14ad7fa0ce Update program counter 
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
 2020-12-12 15:59:14 +09:00
jl7719 3594365a25 Create branch jl7719 
Can test for normal pc incrementing instr
 2020-12-11 19:45:13 +09:00
jl7719 7ffd8fb400 Add testcases and ref outputs for addiu, and, andi 2020-12-11 15:17:43 +09:00
jl7719 04b1ed4fed Update control and memory 
Fixed some errors when testing
 2020-12-10 22:27:08 +09:00
jl7719 84adff2ed1 Update memory 
No longer need the massive memory
 2020-12-10 19:14:16 +09:00
jc4419 3a2fde81b2 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-09 16:27:20 +04:00
jc4419 4b8a56ee2f Fixed if logic for control 2020-12-09 16:24:21 +04:00
jl7719 c5aed43ab4 Update to test each instruction with a small memory 2020-12-09 16:47:58 +09:00
Aadi Desai 6becea322f Update mips_cpu_regfile.v 
Regfile should now compile, write is skipped if $0 is the destination register
 2020-12-08 13:23:08 +00:00
jc4419 9de2b59bbb Updated Harvard, ALU, PC, Control, and Regfile 2020-12-08 01:46:01 +04:00
jc4419 8f5e582f33 Updated ALU - Minor Syntax Fixes 2020-12-07 18:18:19 +04:00
jc4419 2ab6ff12eb Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-07 15:55:12 +04:00
jc4419 9198c4f51b Updated ALU and Control 2020-12-07 15:49:44 +04:00
Aadi Desai d347475b64 Update mips_cpu_regfile.v 
lb, lbu, lh, lhu now  select data according to address alignment
$0 is assigned to 0, may cause an error when written to, unknown.
 2020-12-06 17:42:23 +00:00
jl7719 c5167645e7 Fix overall w.r.t iverilog compiler error 2020-12-06 15:44:58 +09:00
jc4419 a2bcf3ed1b Updated ALU 2020-12-05 23:37:01 +04:00
jl7719 56b5b1aa89 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-04 23:45:16 +09:00
jl7719 411f89110f Add testbench related files 2020-12-04 23:44:48 +09:00
Aadi Desai 847bf92add Fix regfile hazard from storing when inputs change 2020-12-02 19:13:41 +00:00
Aadi Desai f2f8e05010 PC logic updated 
PC now has a delay into instr_mem to match MIPS32 spec and pc resets/initialises to MIPS32 reset vector
 2020-12-02 17:23:28 +00:00
jl7719 10af46a352 Update mips_cpu_memory.v 2020-12-02 23:41:04 +09:00
Ibrahim 64b9d16776 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-02 14:34:35 +00:00
Ibrahim 1f1cb53352 Changed From ALUZero to Cond 2020-12-02 14:33:42 +00:00
Ibrahim a56410ceae - 2020-12-02 14:32:42 +00:00
Aadi Desai 2c967a910b Update mips_cpu_harvard.v 
Fix typo + immediate already fed in via alu_in2
 2020-12-02 14:24:17 +00:00
Ibrahim 888bb7c822 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-02 14:05:59 +00:00
Ibrahim b81c2c0952 Minor sytax corrections 2020-12-02 14:03:16 +00:00
yhp19 d1d64ae747 changed control for aluop and naming 2020-12-02 21:55:17 +08:00
Ibrahim 2a6d87c7b8 Minor sytax corrections 2020-12-02 13:35:47 +00:00
Ibrahim 56dfe9e1e8 Minor sytax corrections 2020-12-02 13:35:00 +00:00
Aadi Desai bd9ae64dc2 Update hardvard.v to match ALU 2020-12-02 13:27:37 +00:00
Ibrahim c4cae70ffc Added ALUZero Output + corrected other syntax errors 2020-12-02 13:12:48 +00:00
Ibrahim 89abb5c1ed Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-02 12:52:37 +00:00
Ibrahim 57d15539a2 Done expect for j type, LWL/R & MLT 2020-12-02 12:51:53 +00:00
yhp19 63b017d552 added control comments 2020-12-02 15:43:30 +08:00
Aadi Desai 27cccc28b8 Added partial loads to regfile 
Partial reads are handled within the ALU
 2020-12-02 01:04:57 +00:00
Aadi Desai 3433337eba Added Regfile 
Missing partial/misaligned loads
 2020-12-01 23:04:43 +00:00
yhp19 4edcb07e1f added control 2020-12-01 15:30:57 +08:00
Aadi Desai 5a72698fec Update mips_cpu_harvard.v 
Add registerv0 testbench line
 2020-11-30 15:36:25 +00:00
Ibrahim ba192442e4 adding immediate back 2020-11-30 14:15:36 +00:00
Ibrahim e4841407e6 ALU - start - questions need addressing 2020-11-30 14:07:33 +00:00
Ibrahim 954a5b47aa
Added shamt to the deconstruction of the instruction 2020-11-30 13:50:04 +00:00
jc4419 02f3f1cbba
Program Counter - Untested 2020-11-30 16:08:58 +04:00
jl7719 841081c152 Update mips_cpu_memory.v 
Change as per constraint
 2020-11-29 17:44:08 +09:00
jl7719 7c9fc23f7e Update mips_cpu_data_memory.v to mips_cpu_memory.v 2020-11-29 17:06:18 +09:00
Aadi Desai 3b183075aa Update mips_cpu_harvard.v 
Added andlink functionality?
 2020-11-29 01:16:33 +00:00
Aadi Desai b5766a15ba Update mips_cpu_harvard.v 
Initial version, connection names to be matched to individual modules
 2020-11-29 01:04:08 +00:00
jl7719 d90b7d3971 Add data memory module 2020-11-27 15:41:14 +09:00
jl7719 e6e4f17afe Add initial coursework deliverables 2020-11-24 14:20:29 +09:00