mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-12-22 21:35:48 +00:00
Create branch jl7719
Can test for normal pc incrementing instr
This commit is contained in:
jl7719
parent
7ffd8fb400
commit
3594365a25
2738
exec/mips_cpu_harvard_tb_add
Normal file
2738
exec/mips_cpu_harvard_tb_add
Normal file
File diff suppressed because it is too large
Load diff
2774
exec/mips_cpu_harvard_tb_addiu
Normal file
2774
exec/mips_cpu_harvard_tb_addiu
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
2738
exec/mips_cpu_harvard_tb_and
Normal file
2738
exec/mips_cpu_harvard_tb_and
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_andi
Normal file
2738
exec/mips_cpu_harvard_tb_andi
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_andiu
Normal file
2738
exec/mips_cpu_harvard_tb_andiu
Normal file
File diff suppressed because it is too large
Load diff
2724
exec/mips_cpu_harvard_tb_cori
Normal file
2724
exec/mips_cpu_harvard_tb_cori
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_o
Normal file
2738
exec/mips_cpu_harvard_tb_o
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_or
Normal file
2738
exec/mips_cpu_harvard_tb_or
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_ori
Normal file
2738
exec/mips_cpu_harvard_tb_ori
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_sll
Normal file
2738
exec/mips_cpu_harvard_tb_sll
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_slti
Normal file
2738
exec/mips_cpu_harvard_tb_slti
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_sltiu
Normal file
2738
exec/mips_cpu_harvard_tb_sltiu
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_sltu
Normal file
2738
exec/mips_cpu_harvard_tb_sltu
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_sra
Normal file
2738
exec/mips_cpu_harvard_tb_sra
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_srl
Normal file
2738
exec/mips_cpu_harvard_tb_srl
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_subu
Normal file
2738
exec/mips_cpu_harvard_tb_subu
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_xor
Normal file
2738
exec/mips_cpu_harvard_tb_xor
Normal file
File diff suppressed because it is too large
Load diff
2738
exec/mips_cpu_harvard_tb_xori
Normal file
2738
exec/mips_cpu_harvard_tb_xori
Normal file
File diff suppressed because it is too large
Load diff
2731
exec/mips_cpu_harvard_tb_xxor
Normal file
2731
exec/mips_cpu_harvard_tb_xxor
Normal file
File diff suppressed because it is too large
Load diff
288
inputs/add.log.txt
Normal file
288
inputs/add.log.txt
Normal file
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@ -0,0 +1,288 @@
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RAM: Loading RAM contents from inputs/add.txt
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ERROR: rtl/mips_cpu_memory.v:33: $readmemh: Unable to open inputs/add.txt for reading.
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byte +bfc00000: 00000000
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byte +bfc00004: 00000000
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byte +bfc00008: 00000000
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byte +bfc0000c: 00000000
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byte +bfc00010: 00000000
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byte +bfc00014: 00000000
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byte +bfc00018: 00000000
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byte +bfc0001c: 00000000
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byte +bfc00020: 00000000
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byte +bfc00024: 00000000
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byte +bfc00028: 00000000
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byte +bfc0002c: 00000000
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byte +bfc00030: 00000000
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byte +bfc00034: 00000000
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byte +bfc00038: 00000000
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byte +bfc0003c: 00000000
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byte +bfc00040: 00000000
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byte +bfc00044: 00000000
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byte +bfc00048: 00000000
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byte +bfc0004c: 00000000
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byte +bfc00050: 00000000
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byte +bfc00054: 00000000
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byte +bfc00058: 00000000
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byte +bfc0005c: 00000000
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byte +bfc00060: 00000000
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byte +bfc00064: 00000000
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byte +bfc00068: 00000000
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byte +bfc0006c: 00000000
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byte +bfc00070: 00000000
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byte +bfc00074: 00000000
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byte +bfc00078: 00000000
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byte +bfc0007c: 00000000
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byte +bfc00080: 00000000
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byte +bfc00084: 00000000
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byte +bfc00088: 00000000
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byte +bfc0008c: 00000000
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byte +bfc00090: 00000000
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byte +bfc00094: 00000000
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byte +bfc00098: 00000000
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byte +bfc0009c: 00000000
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byte +bfc000a0: 00000000
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byte +bfc000a4: 00000000
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byte +bfc000a8: 00000000
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byte +bfc000ac: 00000000
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byte +bfc000b0: 00000000
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byte +bfc000b4: 00000000
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byte +bfc000b8: 00000000
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byte +bfc000bc: 00000000
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byte +bfc000c0: 00000000
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byte +bfc000c4: 00000000
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byte +bfc000c8: 00000000
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byte +bfc000cc: 00000000
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byte +bfc000d0: 00000000
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byte +bfc000d4: 00000000
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byte +bfc000d8: 00000000
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byte +bfc000dc: 00000000
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byte +bfc000e0: 00000000
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byte +bfc000e4: 00000000
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byte +bfc000e8: 00000000
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byte +bfc000ec: 00000000
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byte +bfc000f0: 00000000
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byte +bfc000f4: 00000000
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byte +bfc000f8: 00000000
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byte +bfc000fc: 00000000
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VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
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Initial Reset 0
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Initial Reset 1
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Opcode: xx
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xxxxxxxxxxxxxx
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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Initial Reset 0: Start Program
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New PC from xxxxxxxx to bfc00000
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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Opcode: xx
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xxxxxxxxxxxxxx
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Opcode: xx
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xxxxxxxxxxxxxx
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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New PC from bfc00000 to bfc00000
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New PC from bfc00000 to bfc00004
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00004 to bfc00004
|
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New PC from bfc00004 to bfc00008
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00008 to bfc00008
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New PC from bfc00008 to bfc0000c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0000c to bfc0000c
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New PC from bfc0000c to bfc00010
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00010 to bfc00010
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New PC from bfc00010 to bfc00014
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00014 to bfc00014
|
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New PC from bfc00014 to bfc00018
|
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00018 to bfc00018
|
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New PC from bfc00018 to bfc0001c
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||||
Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0001c to bfc0001c
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New PC from bfc0001c to bfc00020
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00020 to bfc00020
|
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New PC from bfc00020 to bfc00024
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00024 to bfc00024
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New PC from bfc00024 to bfc00028
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00028 to bfc00028
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New PC from bfc00028 to bfc0002c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0002c to bfc0002c
|
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New PC from bfc0002c to bfc00030
|
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00030 to bfc00030
|
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New PC from bfc00030 to bfc00034
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00034 to bfc00034
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New PC from bfc00034 to bfc00038
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00038 to bfc00038
|
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New PC from bfc00038 to bfc0003c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0003c to bfc0003c
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
|
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Opcode: xx
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xxxxxxxxxxxxxx
|
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New PC from bfc0003c to bfc00040
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00040 to bfc00040
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New PC from bfc00040 to bfc00044
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00044 to bfc00044
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New PC from bfc00044 to bfc00048
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Reg File Write data: x
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||||
Reg File Write data: x
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New PC from bfc00048 to bfc00048
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New PC from bfc00048 to bfc0004c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0004c to bfc0004c
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New PC from bfc0004c to bfc00050
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00050 to bfc00050
|
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New PC from bfc00050 to bfc00054
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00054 to bfc00054
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New PC from bfc00054 to bfc00058
|
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00058 to bfc00058
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New PC from bfc00058 to bfc0005c
|
||||
Reg File Write data: x
|
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Reg File Write data: x
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New PC from bfc0005c to bfc0005c
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New PC from bfc0005c to bfc00060
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00060 to bfc00060
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New PC from bfc00060 to bfc00064
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00064 to bfc00064
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New PC from bfc00064 to bfc00068
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00068 to bfc00068
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New PC from bfc00068 to bfc0006c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0006c to bfc0006c
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New PC from bfc0006c to bfc00070
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00070 to bfc00070
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New PC from bfc00070 to bfc00074
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00074 to bfc00074
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New PC from bfc00074 to bfc00078
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00078 to bfc00078
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New PC from bfc00078 to bfc0007c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0007c to bfc0007c
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New PC from bfc0007c to bfc00080
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00080 to bfc00080
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New PC from bfc00080 to bfc00084
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00084 to bfc00084
|
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New PC from bfc00084 to bfc00088
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00088 to bfc00088
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New PC from bfc00088 to bfc0008c
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Reg File Write data: x
|
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Reg File Write data: x
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New PC from bfc0008c to bfc0008c
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New PC from bfc0008c to bfc00090
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00090 to bfc00090
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New PC from bfc00090 to bfc00094
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Reg File Write data: x
|
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Reg File Write data: x
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New PC from bfc00094 to bfc00094
|
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New PC from bfc00094 to bfc00098
|
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00098 to bfc00098
|
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New PC from bfc00098 to bfc0009c
|
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Reg File Write data: x
|
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Reg File Write data: x
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New PC from bfc0009c to bfc0009c
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New PC from bfc0009c to bfc000a0
|
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000a0 to bfc000a0
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New PC from bfc000a0 to bfc000a4
|
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Reg File Write data: x
|
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Reg File Write data: x
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New PC from bfc000a4 to bfc000a4
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New PC from bfc000a4 to bfc000a8
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Reg File Write data: x
|
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Reg File Write data: x
|
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New PC from bfc000a8 to bfc000a8
|
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New PC from bfc000a8 to bfc000ac
|
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Reg File Write data: x
|
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Reg File Write data: x
|
||||
New PC from bfc000ac to bfc000ac
|
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New PC from bfc000ac to bfc000b0
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000b0 to bfc000b0
|
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New PC from bfc000b0 to bfc000b4
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000b4 to bfc000b4
|
||||
New PC from bfc000b4 to bfc000b8
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000b8 to bfc000b8
|
||||
New PC from bfc000b8 to bfc000bc
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000bc to bfc000bc
|
||||
New PC from bfc000bc to bfc000c0
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000c0 to bfc000c0
|
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New PC from bfc000c0 to bfc000c4
|
||||
Reg File Write data: x
|
||||
FATAL: testbench/mips_cpu_harvard_tb.v:47: Simulation did not finish within 100 cycles.
|
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Time: 2000 Scope: mips_cpu_harvard_tb
|
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1
inputs/add.out.txt
Normal file
1
inputs/add.out.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
Time: 2000 Scope: mips_cpu_harvard_tb
|
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4
inputs/addiu.data.txt
Normal file
4
inputs/addiu.data.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
12341234
|
||||
01010101
|
||||
12312312
|
||||
88888888
|
||||
181
inputs/addiu.log.txt
Normal file
181
inputs/addiu.log.txt
Normal file
|
|
@ -0,0 +1,181 @@
|
|||
RAM: Loading RAM contents from inputs/addiu.txt
|
||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/addiu.txt): Not enough words in the file for the requested range [0:63].
|
||||
byte +bfc00000: 3404000a
|
||||
byte +bfc00004: 24820014
|
||||
byte +bfc00008: 00000008
|
||||
byte +bfc0000c: 00000000
|
||||
byte +bfc00010: 00000000
|
||||
byte +bfc00014: 00000000
|
||||
byte +bfc00018: 00000000
|
||||
byte +bfc0001c: 00000000
|
||||
byte +bfc00020: 00000000
|
||||
byte +bfc00024: 00000000
|
||||
byte +bfc00028: 00000000
|
||||
byte +bfc0002c: 00000000
|
||||
byte +bfc00030: 00000000
|
||||
byte +bfc00034: 00000000
|
||||
byte +bfc00038: 00000000
|
||||
byte +bfc0003c: 00000000
|
||||
byte +bfc00040: 00000000
|
||||
byte +bfc00044: 00000000
|
||||
byte +bfc00048: 00000000
|
||||
byte +bfc0004c: 00000000
|
||||
byte +bfc00050: 00000000
|
||||
byte +bfc00054: 00000000
|
||||
byte +bfc00058: 00000000
|
||||
byte +bfc0005c: 00000000
|
||||
byte +bfc00060: 00000000
|
||||
byte +bfc00064: 00000000
|
||||
byte +bfc00068: 00000000
|
||||
byte +bfc0006c: 00000000
|
||||
byte +bfc00070: 00000000
|
||||
byte +bfc00074: 00000000
|
||||
byte +bfc00078: 00000000
|
||||
byte +bfc0007c: 00000000
|
||||
byte +bfc00080: 00000000
|
||||
byte +bfc00084: 00000000
|
||||
byte +bfc00088: 00000000
|
||||
byte +bfc0008c: 00000000
|
||||
byte +bfc00090: 00000000
|
||||
byte +bfc00094: 00000000
|
||||
byte +bfc00098: 00000000
|
||||
byte +bfc0009c: 00000000
|
||||
byte +bfc000a0: 00000000
|
||||
byte +bfc000a4: 00000000
|
||||
byte +bfc000a8: 00000000
|
||||
byte +bfc000ac: 00000000
|
||||
byte +bfc000b0: 00000000
|
||||
byte +bfc000b4: 00000000
|
||||
byte +bfc000b8: 00000000
|
||||
byte +bfc000bc: 00000000
|
||||
byte +bfc000c0: 00000000
|
||||
byte +bfc000c4: 00000000
|
||||
byte +bfc000c8: 00000000
|
||||
byte +bfc000cc: 00000000
|
||||
byte +bfc000d0: 00000000
|
||||
byte +bfc000d4: 00000000
|
||||
byte +bfc000d8: 00000000
|
||||
byte +bfc000dc: 00000000
|
||||
byte +bfc000e0: 00000000
|
||||
byte +bfc000e4: 00000000
|
||||
byte +bfc000e8: 00000000
|
||||
byte +bfc000ec: 00000000
|
||||
byte +bfc000f0: 00000000
|
||||
byte +bfc000f4: 00000000
|
||||
byte +bfc000f8: 00000000
|
||||
byte +bfc000fc: 00000000
|
||||
MEM: Loading MEM contents from inputs/addiu.data.txt
|
||||
WARNING: rtl/mips_cpu_memory.v:42: $readmemh(inputs/addiu.data.txt): Not enough words in the file for the requested range [0:63].
|
||||
byte +00001000: 12341234
|
||||
byte +00001004: 01010101
|
||||
byte +00001008: 12312312
|
||||
byte +0000100c: 88888888
|
||||
byte +00001010: 00000000
|
||||
byte +00001014: 00000000
|
||||
byte +00001018: 00000000
|
||||
byte +0000101c: 00000000
|
||||
byte +00001020: 00000000
|
||||
byte +00001024: 00000000
|
||||
byte +00001028: 00000000
|
||||
byte +0000102c: 00000000
|
||||
byte +00001030: 00000000
|
||||
byte +00001034: 00000000
|
||||
byte +00001038: 00000000
|
||||
byte +0000103c: 00000000
|
||||
byte +00001040: 00000000
|
||||
byte +00001044: 00000000
|
||||
byte +00001048: 00000000
|
||||
byte +0000104c: 00000000
|
||||
byte +00001050: 00000000
|
||||
byte +00001054: 00000000
|
||||
byte +00001058: 00000000
|
||||
byte +0000105c: 00000000
|
||||
byte +00001060: 00000000
|
||||
byte +00001064: 00000000
|
||||
byte +00001068: 00000000
|
||||
byte +0000106c: 00000000
|
||||
byte +00001070: 00000000
|
||||
byte +00001074: 00000000
|
||||
byte +00001078: 00000000
|
||||
byte +0000107c: 00000000
|
||||
byte +00001080: 00000000
|
||||
byte +00001084: 00000000
|
||||
byte +00001088: 00000000
|
||||
byte +0000108c: 00000000
|
||||
byte +00001090: 00000000
|
||||
byte +00001094: 00000000
|
||||
byte +00001098: 00000000
|
||||
byte +0000109c: 00000000
|
||||
byte +000010a0: 00000000
|
||||
byte +000010a4: 00000000
|
||||
byte +000010a8: 00000000
|
||||
byte +000010ac: 00000000
|
||||
byte +000010b0: 00000000
|
||||
byte +000010b4: 00000000
|
||||
byte +000010b8: 00000000
|
||||
byte +000010bc: 00000000
|
||||
byte +000010c0: 00000000
|
||||
byte +000010c4: 00000000
|
||||
byte +000010c8: 00000000
|
||||
byte +000010cc: 00000000
|
||||
byte +000010d0: 00000000
|
||||
byte +000010d4: 00000000
|
||||
byte +000010d8: 00000000
|
||||
byte +000010dc: 00000000
|
||||
byte +000010e0: 00000000
|
||||
byte +000010e4: 00000000
|
||||
byte +000010e8: 00000000
|
||||
byte +000010ec: 00000000
|
||||
byte +000010f0: 00000000
|
||||
byte +000010f4: 00000000
|
||||
byte +000010f8: 00000000
|
||||
byte +000010fc: 00000000
|
||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
||||
Initial Reset 0
|
||||
Initial Reset 1
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Initial Reset 0: Start Program
|
||||
New PC from xxxxxxxx to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 09
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
ALU OP = 0 (ADDU/ADDIU)
|
||||
New PC from bfc00000 to bfc00004
|
||||
Reg File Write data: 30
|
||||
Reg File Write data: 30
|
||||
New PC from bfc00004 to bfc00004
|
||||
Opcode: 09
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
ALU OP = 0 (ADDU/ADDIU)
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
JUMP REGISTER
|
||||
Reg File Write data: 18
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Reg File Write data: 18
|
||||
Reg File Write data: 18
|
||||
TB: CPU Halt; active=0
|
||||
Output:
|
||||
30
|
||||
1
inputs/addiu.out.txt
Normal file
1
inputs/addiu.out.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
30
|
||||
125
inputs/addu.log.txt
Normal file
125
inputs/addu.log.txt
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
RAM: Loading RAM contents from inputs/addu.txt
|
||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/addu.txt): Not enough words in the file for the requested range [0:63].
|
||||
byte +bfc00000: 3404ffff
|
||||
byte +bfc00004: 3405f000
|
||||
byte +bfc00008: 00851021
|
||||
byte +bfc0000c: 00000008
|
||||
byte +bfc00010: 00000000
|
||||
byte +bfc00014: 00000000
|
||||
byte +bfc00018: 00000000
|
||||
byte +bfc0001c: 00000000
|
||||
byte +bfc00020: 00000000
|
||||
byte +bfc00024: 00000000
|
||||
byte +bfc00028: 00000000
|
||||
byte +bfc0002c: 00000000
|
||||
byte +bfc00030: 00000000
|
||||
byte +bfc00034: 00000000
|
||||
byte +bfc00038: 00000000
|
||||
byte +bfc0003c: 00000000
|
||||
byte +bfc00040: 00000000
|
||||
byte +bfc00044: 00000000
|
||||
byte +bfc00048: 00000000
|
||||
byte +bfc0004c: 00000000
|
||||
byte +bfc00050: 00000000
|
||||
byte +bfc00054: 00000000
|
||||
byte +bfc00058: 00000000
|
||||
byte +bfc0005c: 00000000
|
||||
byte +bfc00060: 00000000
|
||||
byte +bfc00064: 00000000
|
||||
byte +bfc00068: 00000000
|
||||
byte +bfc0006c: 00000000
|
||||
byte +bfc00070: 00000000
|
||||
byte +bfc00074: 00000000
|
||||
byte +bfc00078: 00000000
|
||||
byte +bfc0007c: 00000000
|
||||
byte +bfc00080: 00000000
|
||||
byte +bfc00084: 00000000
|
||||
byte +bfc00088: 00000000
|
||||
byte +bfc0008c: 00000000
|
||||
byte +bfc00090: 00000000
|
||||
byte +bfc00094: 00000000
|
||||
byte +bfc00098: 00000000
|
||||
byte +bfc0009c: 00000000
|
||||
byte +bfc000a0: 00000000
|
||||
byte +bfc000a4: 00000000
|
||||
byte +bfc000a8: 00000000
|
||||
byte +bfc000ac: 00000000
|
||||
byte +bfc000b0: 00000000
|
||||
byte +bfc000b4: 00000000
|
||||
byte +bfc000b8: 00000000
|
||||
byte +bfc000bc: 00000000
|
||||
byte +bfc000c0: 00000000
|
||||
byte +bfc000c4: 00000000
|
||||
byte +bfc000c8: 00000000
|
||||
byte +bfc000cc: 00000000
|
||||
byte +bfc000d0: 00000000
|
||||
byte +bfc000d4: 00000000
|
||||
byte +bfc000d8: 00000000
|
||||
byte +bfc000dc: 00000000
|
||||
byte +bfc000e0: 00000000
|
||||
byte +bfc000e4: 00000000
|
||||
byte +bfc000e8: 00000000
|
||||
byte +bfc000ec: 00000000
|
||||
byte +bfc000f0: 00000000
|
||||
byte +bfc000f4: 00000000
|
||||
byte +bfc000f8: 00000000
|
||||
byte +bfc000fc: 00000000
|
||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
||||
Initial Reset 0
|
||||
Initial Reset 1
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Initial Reset 0: Start Program
|
||||
New PC from xxxxxxxx to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00004
|
||||
Reg File Write data: 4294963200
|
||||
Reg File Write data: 4294963200
|
||||
New PC from bfc00004 to bfc00004
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
ALU OP = 0 (ADDU/ADDIU)
|
||||
New PC from bfc00004 to bfc00008
|
||||
Reg File Write data: 4294963199
|
||||
Reg File Write data: 4294963199
|
||||
New PC from bfc00008 to bfc00008
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
ALU OP = 0 (ADDU/ADDIU)
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
JUMP REGISTER
|
||||
Reg File Write data: 4294963199
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Reg File Write data: 4294963199
|
||||
Reg File Write data: 4294963199
|
||||
TB: CPU Halt; active=0
|
||||
Output:
|
||||
4294963199
|
||||
1
inputs/addu.out.txt
Normal file
1
inputs/addu.out.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
4294963199
|
||||
|
|
@ -1 +1 @@
|
|||
8
|
||||
4294963199
|
||||
|
|
@ -1,4 +1,8 @@
|
|||
34040003
|
||||
34050005
|
||||
3404FFFF
|
||||
3405F000
|
||||
00851021
|
||||
00000008
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
123
inputs/and.log.txt
Normal file
123
inputs/and.log.txt
Normal file
|
|
@ -0,0 +1,123 @@
|
|||
RAM: Loading RAM contents from inputs/and.txt
|
||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/and.txt): Not enough words in the file for the requested range [0:63].
|
||||
byte +bfc00000: 3404000a
|
||||
byte +bfc00004: 3405000f
|
||||
byte +bfc00008: 00851024
|
||||
byte +bfc0000c: 00000008
|
||||
byte +bfc00010: 00000000
|
||||
byte +bfc00014: 00000000
|
||||
byte +bfc00018: 00000000
|
||||
byte +bfc0001c: 00000000
|
||||
byte +bfc00020: 00000000
|
||||
byte +bfc00024: 00000000
|
||||
byte +bfc00028: 00000000
|
||||
byte +bfc0002c: 00000000
|
||||
byte +bfc00030: 00000000
|
||||
byte +bfc00034: 00000000
|
||||
byte +bfc00038: 00000000
|
||||
byte +bfc0003c: 00000000
|
||||
byte +bfc00040: 00000000
|
||||
byte +bfc00044: 00000000
|
||||
byte +bfc00048: 00000000
|
||||
byte +bfc0004c: 00000000
|
||||
byte +bfc00050: 00000000
|
||||
byte +bfc00054: 00000000
|
||||
byte +bfc00058: 00000000
|
||||
byte +bfc0005c: 00000000
|
||||
byte +bfc00060: 00000000
|
||||
byte +bfc00064: 00000000
|
||||
byte +bfc00068: 00000000
|
||||
byte +bfc0006c: 00000000
|
||||
byte +bfc00070: 00000000
|
||||
byte +bfc00074: 00000000
|
||||
byte +bfc00078: 00000000
|
||||
byte +bfc0007c: 00000000
|
||||
byte +bfc00080: 00000000
|
||||
byte +bfc00084: 00000000
|
||||
byte +bfc00088: 00000000
|
||||
byte +bfc0008c: 00000000
|
||||
byte +bfc00090: 00000000
|
||||
byte +bfc00094: 00000000
|
||||
byte +bfc00098: 00000000
|
||||
byte +bfc0009c: 00000000
|
||||
byte +bfc000a0: 00000000
|
||||
byte +bfc000a4: 00000000
|
||||
byte +bfc000a8: 00000000
|
||||
byte +bfc000ac: 00000000
|
||||
byte +bfc000b0: 00000000
|
||||
byte +bfc000b4: 00000000
|
||||
byte +bfc000b8: 00000000
|
||||
byte +bfc000bc: 00000000
|
||||
byte +bfc000c0: 00000000
|
||||
byte +bfc000c4: 00000000
|
||||
byte +bfc000c8: 00000000
|
||||
byte +bfc000cc: 00000000
|
||||
byte +bfc000d0: 00000000
|
||||
byte +bfc000d4: 00000000
|
||||
byte +bfc000d8: 00000000
|
||||
byte +bfc000dc: 00000000
|
||||
byte +bfc000e0: 00000000
|
||||
byte +bfc000e4: 00000000
|
||||
byte +bfc000e8: 00000000
|
||||
byte +bfc000ec: 00000000
|
||||
byte +bfc000f0: 00000000
|
||||
byte +bfc000f4: 00000000
|
||||
byte +bfc000f8: 00000000
|
||||
byte +bfc000fc: 00000000
|
||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
||||
Initial Reset 0
|
||||
Initial Reset 1
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Initial Reset 0: Start Program
|
||||
New PC from xxxxxxxx to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00004
|
||||
Reg File Write data: 15
|
||||
Reg File Write data: 15
|
||||
New PC from bfc00004 to bfc00004
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
New PC from bfc00004 to bfc00008
|
||||
Reg File Write data: 10
|
||||
Reg File Write data: 10
|
||||
New PC from bfc00008 to bfc00008
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
JUMP REGISTER
|
||||
Reg File Write data: 10
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Reg File Write data: 10
|
||||
Reg File Write data: 10
|
||||
TB: CPU Halt; active=0
|
||||
Output:
|
||||
10
|
||||
1
inputs/and.out.txt
Normal file
1
inputs/and.out.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
10
|
||||
113
inputs/andi.log.txt
Normal file
113
inputs/andi.log.txt
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
RAM: Loading RAM contents from inputs/andi.txt
|
||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/andi.txt): Not enough words in the file for the requested range [0:63].
|
||||
byte +bfc00000: 34040005
|
||||
byte +bfc00004: 3082000f
|
||||
byte +bfc00008: 00000008
|
||||
byte +bfc0000c: 00000000
|
||||
byte +bfc00010: 00000000
|
||||
byte +bfc00014: 00000000
|
||||
byte +bfc00018: 00000000
|
||||
byte +bfc0001c: 00000000
|
||||
byte +bfc00020: 00000000
|
||||
byte +bfc00024: 00000000
|
||||
byte +bfc00028: 00000000
|
||||
byte +bfc0002c: 00000000
|
||||
byte +bfc00030: 00000000
|
||||
byte +bfc00034: 00000000
|
||||
byte +bfc00038: 00000000
|
||||
byte +bfc0003c: 00000000
|
||||
byte +bfc00040: 00000000
|
||||
byte +bfc00044: 00000000
|
||||
byte +bfc00048: 00000000
|
||||
byte +bfc0004c: 00000000
|
||||
byte +bfc00050: 00000000
|
||||
byte +bfc00054: 00000000
|
||||
byte +bfc00058: 00000000
|
||||
byte +bfc0005c: 00000000
|
||||
byte +bfc00060: 00000000
|
||||
byte +bfc00064: 00000000
|
||||
byte +bfc00068: 00000000
|
||||
byte +bfc0006c: 00000000
|
||||
byte +bfc00070: 00000000
|
||||
byte +bfc00074: 00000000
|
||||
byte +bfc00078: 00000000
|
||||
byte +bfc0007c: 00000000
|
||||
byte +bfc00080: 00000000
|
||||
byte +bfc00084: 00000000
|
||||
byte +bfc00088: 00000000
|
||||
byte +bfc0008c: 00000000
|
||||
byte +bfc00090: 00000000
|
||||
byte +bfc00094: 00000000
|
||||
byte +bfc00098: 00000000
|
||||
byte +bfc0009c: 00000000
|
||||
byte +bfc000a0: 00000000
|
||||
byte +bfc000a4: 00000000
|
||||
byte +bfc000a8: 00000000
|
||||
byte +bfc000ac: 00000000
|
||||
byte +bfc000b0: 00000000
|
||||
byte +bfc000b4: 00000000
|
||||
byte +bfc000b8: 00000000
|
||||
byte +bfc000bc: 00000000
|
||||
byte +bfc000c0: 00000000
|
||||
byte +bfc000c4: 00000000
|
||||
byte +bfc000c8: 00000000
|
||||
byte +bfc000cc: 00000000
|
||||
byte +bfc000d0: 00000000
|
||||
byte +bfc000d4: 00000000
|
||||
byte +bfc000d8: 00000000
|
||||
byte +bfc000dc: 00000000
|
||||
byte +bfc000e0: 00000000
|
||||
byte +bfc000e4: 00000000
|
||||
byte +bfc000e8: 00000000
|
||||
byte +bfc000ec: 00000000
|
||||
byte +bfc000f0: 00000000
|
||||
byte +bfc000f4: 00000000
|
||||
byte +bfc000f8: 00000000
|
||||
byte +bfc000fc: 00000000
|
||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
||||
Initial Reset 0
|
||||
Initial Reset 1
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Initial Reset 0: Start Program
|
||||
New PC from xxxxxxxx to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00000
|
||||
Opcode: 0d
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 0c
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00004
|
||||
Reg File Write data: 5
|
||||
Reg File Write data: 5
|
||||
New PC from bfc00004 to bfc00004
|
||||
Opcode: 0c
|
||||
CTRLREGDST: Rt
|
||||
Memory read disabled
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
JUMP REGISTER
|
||||
Reg File Write data: 0
|
||||
Opcode: 00
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Reg File Write data: 0
|
||||
Reg File Write data: 0
|
||||
TB: CPU Halt; active=0
|
||||
Output:
|
||||
5
|
||||
1
inputs/andi.out.txt
Normal file
1
inputs/andi.out.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
5
|
||||
288
inputs/andiu.log.txt
Normal file
288
inputs/andiu.log.txt
Normal file
|
|
@ -0,0 +1,288 @@
|
|||
RAM: Loading RAM contents from inputs/andiu.txt
|
||||
ERROR: rtl/mips_cpu_memory.v:33: $readmemh: Unable to open inputs/andiu.txt for reading.
|
||||
byte +bfc00000: 00000000
|
||||
byte +bfc00004: 00000000
|
||||
byte +bfc00008: 00000000
|
||||
byte +bfc0000c: 00000000
|
||||
byte +bfc00010: 00000000
|
||||
byte +bfc00014: 00000000
|
||||
byte +bfc00018: 00000000
|
||||
byte +bfc0001c: 00000000
|
||||
byte +bfc00020: 00000000
|
||||
byte +bfc00024: 00000000
|
||||
byte +bfc00028: 00000000
|
||||
byte +bfc0002c: 00000000
|
||||
byte +bfc00030: 00000000
|
||||
byte +bfc00034: 00000000
|
||||
byte +bfc00038: 00000000
|
||||
byte +bfc0003c: 00000000
|
||||
byte +bfc00040: 00000000
|
||||
byte +bfc00044: 00000000
|
||||
byte +bfc00048: 00000000
|
||||
byte +bfc0004c: 00000000
|
||||
byte +bfc00050: 00000000
|
||||
byte +bfc00054: 00000000
|
||||
byte +bfc00058: 00000000
|
||||
byte +bfc0005c: 00000000
|
||||
byte +bfc00060: 00000000
|
||||
byte +bfc00064: 00000000
|
||||
byte +bfc00068: 00000000
|
||||
byte +bfc0006c: 00000000
|
||||
byte +bfc00070: 00000000
|
||||
byte +bfc00074: 00000000
|
||||
byte +bfc00078: 00000000
|
||||
byte +bfc0007c: 00000000
|
||||
byte +bfc00080: 00000000
|
||||
byte +bfc00084: 00000000
|
||||
byte +bfc00088: 00000000
|
||||
byte +bfc0008c: 00000000
|
||||
byte +bfc00090: 00000000
|
||||
byte +bfc00094: 00000000
|
||||
byte +bfc00098: 00000000
|
||||
byte +bfc0009c: 00000000
|
||||
byte +bfc000a0: 00000000
|
||||
byte +bfc000a4: 00000000
|
||||
byte +bfc000a8: 00000000
|
||||
byte +bfc000ac: 00000000
|
||||
byte +bfc000b0: 00000000
|
||||
byte +bfc000b4: 00000000
|
||||
byte +bfc000b8: 00000000
|
||||
byte +bfc000bc: 00000000
|
||||
byte +bfc000c0: 00000000
|
||||
byte +bfc000c4: 00000000
|
||||
byte +bfc000c8: 00000000
|
||||
byte +bfc000cc: 00000000
|
||||
byte +bfc000d0: 00000000
|
||||
byte +bfc000d4: 00000000
|
||||
byte +bfc000d8: 00000000
|
||||
byte +bfc000dc: 00000000
|
||||
byte +bfc000e0: 00000000
|
||||
byte +bfc000e4: 00000000
|
||||
byte +bfc000e8: 00000000
|
||||
byte +bfc000ec: 00000000
|
||||
byte +bfc000f0: 00000000
|
||||
byte +bfc000f4: 00000000
|
||||
byte +bfc000f8: 00000000
|
||||
byte +bfc000fc: 00000000
|
||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
||||
Initial Reset 0
|
||||
Initial Reset 1
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
Initial Reset 0: Start Program
|
||||
New PC from xxxxxxxx to bfc00000
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
New PC from bfc00000 to bfc00000
|
||||
New PC from bfc00000 to bfc00004
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00004 to bfc00004
|
||||
New PC from bfc00004 to bfc00008
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00008 to bfc00008
|
||||
New PC from bfc00008 to bfc0000c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0000c to bfc0000c
|
||||
New PC from bfc0000c to bfc00010
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00010 to bfc00010
|
||||
New PC from bfc00010 to bfc00014
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00014 to bfc00014
|
||||
New PC from bfc00014 to bfc00018
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00018 to bfc00018
|
||||
New PC from bfc00018 to bfc0001c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0001c to bfc0001c
|
||||
New PC from bfc0001c to bfc00020
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00020 to bfc00020
|
||||
New PC from bfc00020 to bfc00024
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00024 to bfc00024
|
||||
New PC from bfc00024 to bfc00028
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00028 to bfc00028
|
||||
New PC from bfc00028 to bfc0002c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0002c to bfc0002c
|
||||
New PC from bfc0002c to bfc00030
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00030 to bfc00030
|
||||
New PC from bfc00030 to bfc00034
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00034 to bfc00034
|
||||
New PC from bfc00034 to bfc00038
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00038 to bfc00038
|
||||
New PC from bfc00038 to bfc0003c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0003c to bfc0003c
|
||||
Opcode: 00
|
||||
CTRLREGDST: Rd
|
||||
Memory read disabled
|
||||
Opcode: xx
|
||||
xxxxxxxxxxxxxx
|
||||
New PC from bfc0003c to bfc00040
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00040 to bfc00040
|
||||
New PC from bfc00040 to bfc00044
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00044 to bfc00044
|
||||
New PC from bfc00044 to bfc00048
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00048 to bfc00048
|
||||
New PC from bfc00048 to bfc0004c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0004c to bfc0004c
|
||||
New PC from bfc0004c to bfc00050
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00050 to bfc00050
|
||||
New PC from bfc00050 to bfc00054
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00054 to bfc00054
|
||||
New PC from bfc00054 to bfc00058
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00058 to bfc00058
|
||||
New PC from bfc00058 to bfc0005c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0005c to bfc0005c
|
||||
New PC from bfc0005c to bfc00060
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00060 to bfc00060
|
||||
New PC from bfc00060 to bfc00064
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00064 to bfc00064
|
||||
New PC from bfc00064 to bfc00068
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00068 to bfc00068
|
||||
New PC from bfc00068 to bfc0006c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0006c to bfc0006c
|
||||
New PC from bfc0006c to bfc00070
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00070 to bfc00070
|
||||
New PC from bfc00070 to bfc00074
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00074 to bfc00074
|
||||
New PC from bfc00074 to bfc00078
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00078 to bfc00078
|
||||
New PC from bfc00078 to bfc0007c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0007c to bfc0007c
|
||||
New PC from bfc0007c to bfc00080
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00080 to bfc00080
|
||||
New PC from bfc00080 to bfc00084
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00084 to bfc00084
|
||||
New PC from bfc00084 to bfc00088
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00088 to bfc00088
|
||||
New PC from bfc00088 to bfc0008c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0008c to bfc0008c
|
||||
New PC from bfc0008c to bfc00090
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00090 to bfc00090
|
||||
New PC from bfc00090 to bfc00094
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00094 to bfc00094
|
||||
New PC from bfc00094 to bfc00098
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc00098 to bfc00098
|
||||
New PC from bfc00098 to bfc0009c
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc0009c to bfc0009c
|
||||
New PC from bfc0009c to bfc000a0
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000a0 to bfc000a0
|
||||
New PC from bfc000a0 to bfc000a4
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000a4 to bfc000a4
|
||||
New PC from bfc000a4 to bfc000a8
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000a8 to bfc000a8
|
||||
New PC from bfc000a8 to bfc000ac
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000ac to bfc000ac
|
||||
New PC from bfc000ac to bfc000b0
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000b0 to bfc000b0
|
||||
New PC from bfc000b0 to bfc000b4
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000b4 to bfc000b4
|
||||
New PC from bfc000b4 to bfc000b8
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000b8 to bfc000b8
|
||||
New PC from bfc000b8 to bfc000bc
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000bc to bfc000bc
|
||||
New PC from bfc000bc to bfc000c0
|
||||
Reg File Write data: x
|
||||
Reg File Write data: x
|
||||
New PC from bfc000c0 to bfc000c0
|
||||
New PC from bfc000c0 to bfc000c4
|
||||
Reg File Write data: x
|
||||
FATAL: testbench/mips_cpu_harvard_tb.v:47: Simulation did not finish within 100 cycles.
|
||||
Time: 2000 Scope: mips_cpu_harvard_tb
|
||||
1
inputs/andiu.out.txt
Normal file
1
inputs/andiu.out.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
Time: 2000 Scope: mips_cpu_harvard_tb
|
||||
|
|
@ -1,8 +1,7 @@
|
|||
34040005
|
||||
34050005
|
||||
10850003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
50004043
|
||||
50005043
|
||||
20005801
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
34040003
|
||||
04810003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
30004043
|
||||
20001840
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
34040003
|
||||
04910004
|
||||
00000000
|
||||
24420001
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
03E00008
|
||||
30004043
|
||||
30001940
|
||||
00006C42
|
||||
10002442
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
34040003
|
||||
1C800003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
30004043
|
||||
200008C1
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
3C05FFFF
|
||||
18800003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
FFFF4043
|
||||
20000881
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
3C05FFFF
|
||||
04800003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
FFFF4043
|
||||
20000840
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
3C05FFFF
|
||||
04900004
|
||||
00000000
|
||||
24420001
|
||||
00000000
|
||||
00000008
|
||||
34020001
|
||||
03E00008
|
||||
FFFF4043
|
||||
20000940
|
||||
00006C42
|
||||
10002442
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
34040003
|
||||
34040005
|
||||
14850003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
30004043
|
||||
50005043
|
||||
20005841
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
|
|
|||
|
|
@ -267,7 +267,7 @@ ori $4,$0,3
|
|||
sll $2,$4,2
|
||||
jr $0
|
||||
|
||||
register 0 = 16
|
||||
register 0 = 12
|
||||
|
||||
34040003
|
||||
00041080
|
||||
|
|
|
|||
1
inputs/or.ref.txt
Normal file
1
inputs/or.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
7
|
||||
1
inputs/ori.ref.txt
Normal file
1
inputs/ori.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
8
|
||||
|
|
@ -1,2 +1,8 @@
|
|||
34040003
|
||||
34020008
|
||||
00000008
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
|
|
@ -5,7 +5,9 @@ Hex code
|
|||
Reference Output
|
||||
================
|
||||
|
||||
ADDIU Add immediate unsigned (no overflow)
|
||||
== ADDIU Add immediate unsigned (no overflow) ==
|
||||
|
||||
|
||||
|
||||
== ADDU Add unsigned (no overflow) ==
|
||||
|
||||
|
|
@ -25,169 +27,142 @@ JR $0
|
|||
|
||||
register_v0 = 8
|
||||
|
||||
==AND Bitwise and==
|
||||
|
||||
ORI $5,$0,0xCCCC
|
||||
LUI $5,0xCCCC
|
||||
ORI $4,$0,0xAAAA
|
||||
LUI $4,0xAAAA
|
||||
AND $2,$4,$5
|
||||
JR $0
|
||||
== AND Bitwise and ==
|
||||
|
||||
register_v0 = 0x88888888
|
||||
|
||||
==ANDI Bitwise and immediate==
|
||||
|
||||
ORI $4,$0,0xAAAA
|
||||
LUI $4,0xAAAA
|
||||
ANDI $2,$4,0xCCCC
|
||||
JR $0
|
||||
|
||||
register_v0 = 0x00008888
|
||||
ANDI Bitwise and immediate
|
||||
|
||||
==BEQ Branch on equal==
|
||||
|
||||
ORI $4,$0,5
|
||||
ORI $5,$0,5
|
||||
BEQ $4,$5,3
|
||||
NOP
|
||||
BEQ $4,$5,2
|
||||
ADDIU $6,$6,0
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
34040005
|
||||
34050005
|
||||
10850003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
50004043
|
||||
50005043
|
||||
20005801
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
|
||||
==BGEZ Branch on greater than or equal to zero==
|
||||
|
||||
ORI $4,$0,3
|
||||
BGEZ $4,3
|
||||
NOP
|
||||
BGEZ $4,2
|
||||
ADDIU $6,$6,0
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
34040003
|
||||
04810003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
30004043
|
||||
20001840
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
==BGEZAL Branch on non-negative (>=0) and link==
|
||||
|
||||
ORI $4,$0,3
|
||||
BGEZAL $4,4
|
||||
NOP
|
||||
BGEZAL $4,3
|
||||
ADDIU $6,$6,0
|
||||
ADDIU $2,$2,1
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $31
|
||||
|
||||
34040003
|
||||
04910004
|
||||
00000000
|
||||
24420001
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
03E00008
|
||||
30004043
|
||||
30001940
|
||||
00006C42
|
||||
10002442
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 2
|
||||
|
||||
|
||||
==BGTZ Branch on greater than zero==
|
||||
|
||||
ORI $4,$0,3
|
||||
BGTZ $4,3
|
||||
NOP
|
||||
BGTZ $4,2
|
||||
ADDIU $6,$6,0
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
34040003
|
||||
1C800003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
30004043
|
||||
200008C1
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
==BLEZ Branch on less than or equal to zero==
|
||||
|
||||
LUI $4,0xFFFF
|
||||
BLEZ $4,3
|
||||
NOP
|
||||
ORI $4,$0,-1
|
||||
BLEZ $4,2
|
||||
ADDIU $6,$6,0
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
3C05FFFF
|
||||
18800003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
FFFF4043
|
||||
20000881
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
==BLTZ Branch on less than zero==
|
||||
|
||||
LUI $4,0xFFFF
|
||||
BLTZ $4,3
|
||||
NOP
|
||||
ORI $4,$0,-1
|
||||
BLTZ $4,2
|
||||
ADDIU $6,$6,0
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
3C05FFFF
|
||||
04800003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
FFFF4043
|
||||
20000840
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
==BLTZAL Branch on less than zero and link==
|
||||
|
||||
LUI $4,0xFFFF
|
||||
BLTZAL $4,4
|
||||
NOP
|
||||
ORI $4,$0,-1
|
||||
BLTZAL $4,3
|
||||
ADDIU $6,$6,0
|
||||
ADDIU $2,$2,1
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $31
|
||||
|
||||
3C05FFFF
|
||||
04900004
|
||||
00000000
|
||||
24420001
|
||||
00000000
|
||||
00000008
|
||||
34020001
|
||||
03E00008
|
||||
FFFF4043
|
||||
20000940
|
||||
00006C42
|
||||
10002442
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 2
|
||||
|
||||
|
|
@ -195,132 +170,28 @@ register_v0 = 2
|
|||
|
||||
ORI $4,$0,3
|
||||
ORI $5,$0,5
|
||||
BNE $4,$5,3
|
||||
NOP
|
||||
BNE $4,$5,2
|
||||
ADDIU $6, $6, 0
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
JR $
|
||||
|
||||
34040003
|
||||
34040005
|
||||
14850003
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
==DIV Divide== //May need other testcases for -ve/+ve, -ve/-ve
|
||||
|
||||
ORI $4,$0,3
|
||||
ORI $5,$0,9
|
||||
DIV $5,$4
|
||||
MFHI $4
|
||||
MFLO $5
|
||||
ADDU $2,$4,$5
|
||||
JR $0
|
||||
|
||||
register_v0 = 3
|
||||
|
||||
==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
|
||||
|
||||
LUI $4,0x8000
|
||||
ORI $5,$0,2
|
||||
DIV $4,$5
|
||||
MFHI $4
|
||||
MFLO $5
|
||||
ADDU $2,$4,$5
|
||||
JR $0
|
||||
|
||||
register_v0 = 0x40000000
|
||||
|
||||
==J Jump==
|
||||
|
||||
J 4
|
||||
NOP
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
08000004
|
||||
00000000
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00000008
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
==JALR Jump and link register==
|
||||
|
||||
ORI $5,$0,0x001C
|
||||
LUI $5,0xBFC0
|
||||
JALR $4,$5
|
||||
NOP
|
||||
ADDIU $2,$2,1
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $4
|
||||
|
||||
3405001C
|
||||
3C05BCF0
|
||||
00A02009
|
||||
00000000
|
||||
24420001
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
00800008
|
||||
|
||||
|
||||
register_v0 = 2
|
||||
|
||||
==JAL Jump and link==
|
||||
|
||||
JAL 5
|
||||
NOP
|
||||
ADDIU $2,$2,1
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $31
|
||||
|
||||
0C000005
|
||||
00000000
|
||||
24420001
|
||||
00000008
|
||||
00000000
|
||||
34020001
|
||||
03E00008
|
||||
|
||||
register_v0 = 2
|
||||
|
||||
==JR Jump register==
|
||||
|
||||
ORI $5,$0,0x0014
|
||||
LUI $5,0xBFC0
|
||||
JR $5
|
||||
NOP
|
||||
JR $0
|
||||
NOP
|
||||
ORI $2,$0,1
|
||||
JR $0
|
||||
|
||||
34050014
|
||||
3C05BCF0
|
||||
00A00008
|
||||
00000000
|
||||
00000008
|
||||
34020001
|
||||
00000008
|
||||
30004043
|
||||
50005043
|
||||
20005841
|
||||
00006C42
|
||||
80000000
|
||||
10002043
|
||||
80000000
|
||||
|
||||
register_v0 = 1
|
||||
|
||||
DIV Divide
|
||||
DIVU Divide unsigned
|
||||
J Jump
|
||||
JALR Jump and link register
|
||||
JAL Jump and link
|
||||
JR Jump register
|
||||
LB Load byte
|
||||
LBU Load byte unsigned
|
||||
LH Load half-word
|
||||
|
|
@ -329,55 +200,25 @@ LUI Load upper immediate
|
|||
LW Load word
|
||||
LWL Load word left
|
||||
LWR Load word right
|
||||
|
||||
// DIVU Divide unsigned
|
||||
|
||||
// DIV Divide
|
||||
|
||||
//MFHI Move from Hi
|
||||
|
||||
//MFLO Move from lo
|
||||
|
||||
//MTHI Move to HI
|
||||
|
||||
//MTLO Move to LO
|
||||
|
||||
//MULT Multiply**
|
||||
|
||||
//MULTU Multiply unsigned**
|
||||
|
||||
//OR Bitwise or
|
||||
|
||||
//ORI Bitwise or immediate
|
||||
|
||||
//SB Store byte
|
||||
|
||||
//SH Store half-word**
|
||||
|
||||
//SLL Shift left logical
|
||||
|
||||
//SLLV Shift left logical variable **
|
||||
|
||||
//SLT Set on less than (signed)
|
||||
|
||||
//SLTI Set on less than immediate (signed)
|
||||
|
||||
//SLTIU Set on less than immediate unsigned
|
||||
|
||||
//SLTU Set on less than unsigned
|
||||
|
||||
//SRA Shift right arithmetic
|
||||
|
||||
//SRAV Shift right arithmetic**
|
||||
|
||||
//SRL Shift right logical
|
||||
|
||||
//SRLV Shift right logical variable**
|
||||
|
||||
//SUBU Subtract unsigned
|
||||
|
||||
//SW Store word
|
||||
|
||||
//XOR Bitwise exclusive or
|
||||
|
||||
//XORI Bitwise exclusive or immediate
|
||||
MTHI Move to HI
|
||||
MTLO Move to LO
|
||||
MULT Multiply
|
||||
MULTU Multiply unsigned
|
||||
OR Bitwise or
|
||||
ORI Bitwise or immediate
|
||||
SB Store byte
|
||||
SH Store half-word
|
||||
SLL Shift left logical
|
||||
SLLV Shift left logical variable
|
||||
SLT Set on less than (signed)
|
||||
SLTI Set on less than immediate (signed)
|
||||
SLTIU Set on less than immediate unsigned
|
||||
SLTU Set on less than unsigned
|
||||
SRA Shift right arithmetic
|
||||
SRAV Shift right arithmetic
|
||||
SRL Shift right logical
|
||||
SRLV Shift right logical variable
|
||||
SUBU Subtract unsigned
|
||||
SW Store word
|
||||
XOR Bitwise exclusive or
|
||||
XORI Bitwise exclusive or immediate
|
||||
1
inputs/sll.ref.txt
Normal file
1
inputs/sll.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
16
|
||||
1
inputs/slti.ref.txt
Normal file
1
inputs/slti.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
0
|
||||
1
inputs/sltiu.ref.txt
Normal file
1
inputs/sltiu.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
0
|
||||
1
inputs/sltu.ref.txt
Normal file
1
inputs/sltu.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
0
|
||||
1
inputs/sra.ref.txt
Normal file
1
inputs/sra.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
-536870912
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
34040001
|
||||
00041003
|
||||
3404000C
|
||||
00041083
|
||||
00000008
|
||||
|
|
|
|||
0
inputs/srav.ref.txt
Normal file
0
inputs/srav.ref.txt
Normal file
1
inputs/srl.ref.txt
Normal file
1
inputs/srl.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
8
|
||||
1
inputs/subu.ref.txt
Normal file
1
inputs/subu.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
2
|
||||
1
inputs/temp.ref.txt
Normal file
1
inputs/temp.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
59
|
||||
8
inputs/temp.txt
Normal file
8
inputs/temp.txt
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
34020008
|
||||
00000008
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
1
inputs/xor.ref.txt
Normal file
1
inputs/xor.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
7
|
||||
1
inputs/xori.ref.txt
Normal file
1
inputs/xori.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
10
|
||||
|
|
@ -1,3 +1,5 @@
|
|||
34040005
|
||||
38820002
|
||||
3882000F
|
||||
00000008
|
||||
00000000
|
||||
00000000
|
||||
|
|
@ -83,13 +83,17 @@ assign rt = Instr[20:16];
|
|||
|
||||
always @(*) begin
|
||||
//CtrlRegDst logic
|
||||
$display("Opcode: %h", op);
|
||||
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin
|
||||
CtrlRegDst = 2'd0; //Write address comes from rt
|
||||
$display("CTRLREGDST: Rt");
|
||||
end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
|
||||
CtrlRegDst = 2'd1; //Write address comes from rd
|
||||
$display("CTRLREGDST: Rd");
|
||||
end else if (op == JAL)begin
|
||||
CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
|
||||
end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
|
||||
$display("CTRLREGDST: Link");
|
||||
end else begin CtrlRegDst = 1'bx; $display("xxxxxxxxxxxxxx");end//Not all instructions are encompassed so, added incase for debug purposes
|
||||
|
||||
//CtrlPC logic
|
||||
if(ALUCond && ((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL)))))begin
|
||||
|
|
@ -105,9 +109,11 @@ always @(*) begin
|
|||
if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR))begin
|
||||
CtrlMemRead = 1;//Memory is read enabled
|
||||
CtrlMemtoReg = 2'd1;//write data port of memory is fed from data memory
|
||||
$display("Memory read enabled");
|
||||
end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MTHI) || (funct==MTLO) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin
|
||||
CtrlMemRead = 0;//Memory is read disabled
|
||||
CtrlMemtoReg = 2'd0;//write data port of memory is fed from ALURes
|
||||
$display("Memory read disabled");
|
||||
end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)))begin
|
||||
CtrlMemtoReg = 2'd2;//write data port of memory is fed from PC + 8
|
||||
end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
|
||||
|
|
@ -115,6 +121,7 @@ always @(*) begin
|
|||
//CtrlALUOp Logic
|
||||
if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
|
||||
CtrlALUOp = 5'd0; //ADD from ALUOps
|
||||
$display("ALU OP = 0 (ADDU/ADDIU)");
|
||||
end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin
|
||||
CtrlALUOp = 5'd4;//AND from ALUOps
|
||||
end else if(op==BEQ) begin
|
||||
|
|
@ -165,6 +172,7 @@ always @(*) begin
|
|||
CtrlALUOp = 5'd1;//SUB from ALUOps
|
||||
end else if((op==XORI) || ((op==SPECIAL)&&(funct==XOR)))begin
|
||||
CtrlALUOp = 5'd6;//XOR from ALUOps
|
||||
$display("ALU Op = 6 (XOR)");
|
||||
end else begin
|
||||
CtrlALUOp = 5'bxxxxx;
|
||||
end
|
||||
|
|
@ -189,7 +197,7 @@ always @(*) begin
|
|||
end else begin CtrlALUSrc = 1'bx;end
|
||||
|
||||
//CtrlRegWrite logic
|
||||
if ((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin
|
||||
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin
|
||||
CtrlRegWrite = 1;//The Registers are Write Enabled
|
||||
end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
|
||||
end
|
||||
|
|
|
|||
|
|
@ -21,57 +21,38 @@ module mips_cpu_harvard(
|
|||
);
|
||||
|
||||
always_comb begin
|
||||
instr_address = out_pc_out;
|
||||
instr_address = in_pc_in;
|
||||
data_address = out_ALURes;
|
||||
data_write = out_MemWrite;
|
||||
data_read = out_MemRead;
|
||||
data_writedata = out_readdata2;
|
||||
end
|
||||
|
||||
logic[31:0] in_pc_in;
|
||||
logic[4:0] in_readreg1;
|
||||
logic[4:0] in_readreg2;
|
||||
logic[4:0] in_writereg;
|
||||
logic[31:0] in_writedata;
|
||||
logic[31:0] in_pc_in, out_pc_out = 32'hBFC00000, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata;
|
||||
logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp;
|
||||
logic[5:0] in_opcode;
|
||||
logic[31:0] in_B;
|
||||
logic out_ALUCond, out_RegWrite, out_ALUSrc, out_MemWrite, out_MemRead;
|
||||
logic[1:0] out_RegDst, out_PC, out_MemtoReg;
|
||||
|
||||
assign in_readreg1 = instr_readdata[25:21];
|
||||
assign in_readreg2 = instr_readdata[20:16];
|
||||
assign in_opcode = instr_readdata[31:26];
|
||||
|
||||
always_comb begin
|
||||
|
||||
in_readreg1 = instr_readdata[25:21];
|
||||
in_readreg2 = instr_readdata[20:16];
|
||||
in_opcode = instr_readdata[31:26];
|
||||
|
||||
//Picking what the next value of PC should be.
|
||||
case(out_PC)
|
||||
2'd0: begin
|
||||
in_pc_in = out_pc_out + 32'd4;//No branch or jump or load, so no delay slot.
|
||||
end
|
||||
2'd1: begin
|
||||
in_pc_in = //help
|
||||
end
|
||||
2'd2: begin
|
||||
in_pc_in = //my brain hurts
|
||||
end
|
||||
2'd3: begin
|
||||
in_pc_in = //I need to sleep......
|
||||
end
|
||||
endcase
|
||||
|
||||
//Picking what register should be written to.
|
||||
//Picking what register should be written to.
|
||||
case(out_RegDst)
|
||||
2'd0:begin
|
||||
2'd0: begin
|
||||
in_writereg = instr_readdata[20:16];//GPR rt
|
||||
end
|
||||
2'd1:begin
|
||||
2'd1: begin
|
||||
in_writereg = instr_readdata[15:11];//GPR rd
|
||||
end
|
||||
2'd2:begin
|
||||
2'd2: begin
|
||||
in_writereg = 5'd31;//Link Register 31.
|
||||
end
|
||||
endcase
|
||||
|
||||
//Picking which output should be written to regfile.
|
||||
//Picking which output should be written to regfile.
|
||||
case(out_MemtoReg)
|
||||
2'd0:begin
|
||||
in_writedata = out_ALURes;//Output from ALU Result.
|
||||
|
|
@ -84,7 +65,7 @@ always_comb begin
|
|||
end
|
||||
endcase
|
||||
|
||||
//Picking which output should be taken as the second operand for ALU.
|
||||
//Picking which output should be taken as the second operand for ALU.
|
||||
case(out_ALUSrc)
|
||||
1'b1:begin
|
||||
in_B = {{16{instr_readdata[15]}},instr_readdata[15:0]};//Output from the 16-bit immediate values sign extened to 32bits.
|
||||
|
|
@ -99,9 +80,11 @@ pc pc(
|
|||
//PC inputs
|
||||
.clk(clk),//clk taken from the Standard signals
|
||||
.rst(reset),//clk taken from the Standard signals
|
||||
.pc_in(in_pc_in),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
|
||||
.pc_ctrl(out_PC),
|
||||
.pc_in(out_pc_out),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
|
||||
//PC outputs
|
||||
.pc_out(out_pc_out)//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory.
|
||||
.pc_out(in_pc_in),//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory.
|
||||
.active(active)
|
||||
);
|
||||
|
||||
mips_cpu_control control( //instance of the 'mips_cpu_control' module called 'control' in top level 'harvard'
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ module mips_cpu_memory(
|
|||
|
||||
);
|
||||
parameter RAM_INIT_FILE = "";
|
||||
|
||||
parameter MEM_INIT_FILE = "";
|
||||
reg [31:0] data_memory [0:63];
|
||||
reg [31:0] instr_memory [0:63];
|
||||
|
||||
|
|
@ -36,10 +36,21 @@ module mips_cpu_memory(
|
|||
for (integer j = 0; j<$size(instr_memory); j++) begin
|
||||
$display("byte +%h: %h", 32'hBFC00000+j*4, instr_memory[j]);
|
||||
end
|
||||
|
||||
if (MEM_INIT_FILE != "") begin
|
||||
$display("MEM: Loading MEM contents from %s", MEM_INIT_FILE);
|
||||
$readmemh(MEM_INIT_FILE, data_memory);
|
||||
end else begin
|
||||
$display("MEM FILE NOT GIVEN");
|
||||
end
|
||||
|
||||
for (integer k = 0; k<$size(data_memory); k++) begin
|
||||
$display("byte +%h: %h", 32'h00001000+k*4, data_memory[k]);
|
||||
end
|
||||
end
|
||||
|
||||
//Combinatorial read path for data and instruction.
|
||||
assign data_readdata = data_read ? data_memory[data_address>>2] : 32'hxxxxxxxx;
|
||||
assign data_readdata = data_read ? data_memory[(data_address-32'h00001000)>>2] : 32'hxxxxxxxx;
|
||||
assign instr_readdata = (instr_address >= 32'hBFC00000 && instr_address < 32'hBFC00000+$size(instr_memory)) ? instr_memory[(instr_address-32'hBFC00000)>>2] : 32'hxxxxxxxx;
|
||||
|
||||
|
||||
|
|
@ -54,3 +65,4 @@ module mips_cpu_memory(
|
|||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,27 +1,46 @@
|
|||
module pc(
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic[1:0] pc_ctrl,
|
||||
input logic[31:0] pc_in,
|
||||
output logic[31:0] pc_out
|
||||
input logic[4:0] rs,
|
||||
output logic[31:0] pc_out,
|
||||
output logic active
|
||||
);
|
||||
|
||||
reg[31:0] pc_curr;
|
||||
reg [31:0] pc_curr;
|
||||
|
||||
initial begin
|
||||
pc_curr = 32'hBFC00000;
|
||||
pc_out = pc_in;
|
||||
end // initial
|
||||
|
||||
always_comb begin
|
||||
if (rst) begin
|
||||
pc_curr = 32'hBFC00000;
|
||||
end else begin
|
||||
pc_curr = pc_in;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
pc_out <= pc_curr;
|
||||
if (rst) begin
|
||||
active <= 1;
|
||||
pc_out <= 32'hBFC00000;
|
||||
end else if (pc_out != 32'd0) begin
|
||||
active <= active;
|
||||
case(pc_ctrl)
|
||||
2'd0: begin
|
||||
pc_curr <= pc_out;
|
||||
pc_out <= pc_curr + 32'd4;//No branch or jump or load, so no delay slot.
|
||||
$display("New PC from %h to %h", pc_curr, pc_out);
|
||||
end
|
||||
2'd1: begin
|
||||
pc_out <= pc_in;//Branches
|
||||
end
|
||||
2'd2: begin
|
||||
pc_out <= pc_in;//Jumps
|
||||
end
|
||||
2'd3: begin
|
||||
$display("JUMP REGISTER");
|
||||
pc_out <= 32'd0;//Jumps using register
|
||||
end
|
||||
endcase
|
||||
end else if (pc_out == 32'd0) begin
|
||||
active <= 0;
|
||||
//$display("CPU Halt");
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // pc
|
||||
21
test/test_mips_cpu_custom.sh
Normal file
21
test/test_mips_cpu_custom.sh
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
#!/bin/bash
|
||||
|
||||
bash test/test_mips_cpu_harvard.sh rtl addu #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl addiu #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl ori #Pass
|
||||
#bash test/test_mips_cpu_harvard.sh rtl sw
|
||||
bash test/test_mips_cpu_harvard.sh rtl and #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl andi #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl or #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl xor #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl xori #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl sll
|
||||
bash test/test_mips_cpu_harvard.sh rtl slti
|
||||
bash test/test_mips_cpu_harvard.sh rtl sltiu #Pass
|
||||
#bash test/test_mips_cpu_harvard.sh rtl slt # missing
|
||||
bash test/test_mips_cpu_harvard.sh rtl sltu #Pass
|
||||
bash test/test_mips_cpu_harvard.sh rtl sra
|
||||
bash test/test_mips_cpu_harvard.sh rtl srav
|
||||
bash test/test_mips_cpu_harvard.sh rtl srl
|
||||
bash test/test_mips_cpu_harvard.sh rtl srlv
|
||||
bash test/test_mips_cpu_harvard.sh rtl subu #Pass
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
#**Delete command for windows before submission**
|
||||
#rm inputs/*.log.txt inputs/*.ref.txt
|
||||
#rm inputs/*.log.txt inputs/*.out.txt
|
||||
|
||||
# Source File & Source Directory Parsing
|
||||
SRC_DIR=${1?Error: no source directory given in argument}; # e.g. rtl
|
||||
|
|
@ -30,7 +30,7 @@ then
|
|||
#/mnt/c/Windows/System32/cmd.exe /C \
|
||||
iverilog -Wall -g2012 \
|
||||
-s mips_cpu_harvard_tb \
|
||||
-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\" \
|
||||
-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\"
|
||||
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
|
||||
${SRC} 2> /dev/null
|
||||
/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${TESTCASE}.log.txt; # log file for debugging (contains $display)
|
||||
|
|
@ -49,8 +49,9 @@ else
|
|||
iverilog -Wall -g2012 \
|
||||
-s mips_cpu_harvard_tb \
|
||||
-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
|
||||
-P mips_cpu_harvard_tb.MEM_INIT_FILE=\"inputs/${INSTR}.data.txt\" \
|
||||
-o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
|
||||
${SRC} 2> /dev/null
|
||||
${SRC} #2> /dev/null
|
||||
/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR} &> ./inputs/${INSTR}.log.txt; # log file for debugging (contains $display)
|
||||
echo "$(tail -1 ./inputs/${INSTR}.log.txt)" > ./inputs/${INSTR}.out.txt; # register v0 output to compare with reference
|
||||
if diff -w ./inputs/${INSTR}.out.txt ./inputs/${INSTR}.ref.txt &> /dev/null # compare
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
module mips_cpu_harvard_tb;
|
||||
|
||||
parameter RAM_INIT_FILE = "inputs/addu.txt";
|
||||
parameter RAM_INIT_FILE = "inputs/addiu.txt";
|
||||
parameter MEM_INIT_FILE = "inputs/addiu.data.txt";
|
||||
parameter TIMEOUT_CYCLES = 100;
|
||||
|
||||
logic clk, clk_enable, reset, active, data_read, data_write;
|
||||
logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
|
||||
|
||||
mips_cpu_memory #(RAM_INIT_FILE) ramInst(
|
||||
mips_cpu_memory #(RAM_INIT_FILE, MEM_INIT_FILE) ramInst(
|
||||
.clk(clk),
|
||||
.data_address(data_address),
|
||||
.data_write(data_write),
|
||||
|
|
@ -33,6 +34,8 @@ module mips_cpu_harvard_tb;
|
|||
|
||||
// Generate clock
|
||||
initial begin
|
||||
$dumpfile("mips_cpu_harvard.vcd");
|
||||
$dumpvars(0,mips_cpu_harvard_tb);
|
||||
clk=0;
|
||||
|
||||
repeat (TIMEOUT_CYCLES) begin
|
||||
|
|
@ -63,12 +66,15 @@ module mips_cpu_harvard_tb;
|
|||
else $display("TB: CPU did not set active=1 after reset.");
|
||||
|
||||
while (active) begin
|
||||
//$display("Clk: %d", clk);
|
||||
@(posedge clk);
|
||||
$display("Register v0: %d", register_v0);
|
||||
//$display("Register v0: %d", register_v0);
|
||||
$display("Reg File Write data: %d", cpuInst.in_writedata);
|
||||
end
|
||||
|
||||
$display("TB: finished; active=0");
|
||||
$display("Output: %d", register_v0);
|
||||
@(posedge clk);
|
||||
$display("TB: CPU Halt; active=0");
|
||||
$display("Output:");
|
||||
$display("%d",register_v0);
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in a new issue