supleed2/ELEC50010-IAC-CW
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ELEC50010-IAC-CW/exec/mips_cpu_harvard_tb_ori
jl7719 3594365a25 Create branch jl7719 
Can test for normal pc incrementing instr
2020-12-11 19:45:13 +09:00

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#! /usr/local/iverilog/bin/vvp
:ivl_version "11.0 (devel)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2009.vpi";
S_000000000112c010 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_000000000112a580 .scope module, "mips_cpu_harvard_tb" "mips_cpu_harvard_tb" 3 1;
.timescale 0 0;
P_00000000010f3ef0 .param/str "RAM_INIT_FILE" 0 3 3, "inputs/ori.txt";
P_00000000010f3f28 .param/l "TIMEOUT_CYCLES" 0 3 4, +C4<00000000000000000000000001100100>;
v0000000001184fa0_0 .net "active", 0 0, v0000000001129380_0; 1 drivers
v0000000001184b40_0 .var "clk", 0 0;
v0000000001186800_0 .var "clk_enable", 0 0;
v0000000001184d20_0 .net "data_address", 31 0, v0000000001129e20_0; 1 drivers
v00000000011859a0_0 .net "data_read", 0 0, v0000000001129ec0_0; 1 drivers
v00000000011863a0_0 .net "data_readdata", 31 0, L_0000000001184be0; 1 drivers
v0000000001185040_0 .net "data_write", 0 0, v0000000001129f60_0; 1 drivers
v0000000001186300_0 .net "data_writedata", 31 0, v000000000112a1e0_0; 1 drivers
v0000000001186080_0 .net "instr_address", 31 0, v0000000001184070_0; 1 drivers
v0000000001184c80_0 .net "instr_readdata", 31 0, L_0000000001185180; 1 drivers
v00000000011869e0_0 .net "register_v0", 31 0, L_000000000111b8c0; 1 drivers
v00000000011868a0_0 .var "reset", 0 0;
S_000000000112b580 .scope module, "cpuInst" "mips_cpu_harvard" 3 19, 4 1 0, S_000000000112a580;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "reset";
.port_info 2 /OUTPUT 1 "active";
.port_info 3 /OUTPUT 32 "register_v0";
.port_info 4 /INPUT 1 "clk_enable";
.port_info 5 /OUTPUT 32 "instr_address";
.port_info 6 /INPUT 32 "instr_readdata";
.port_info 7 /OUTPUT 32 "data_address";
.port_info 8 /OUTPUT 1 "data_write";
.port_info 9 /OUTPUT 1 "data_read";
.port_info 10 /OUTPUT 32 "data_writedata";
.port_info 11 /INPUT 32 "data_readdata";
v000000000112a280_0 .net "active", 0 0, v0000000001129380_0; alias, 1 drivers
v0000000001129ce0_0 .net "clk", 0 0, v0000000001184b40_0; 1 drivers
v0000000001129d80_0 .net "clk_enable", 0 0, v0000000001186800_0; 1 drivers
v0000000001129e20_0 .var "data_address", 31 0;
v0000000001129ec0_0 .var "data_read", 0 0;
v000000000112a000_0 .net "data_readdata", 31 0, L_0000000001184be0; alias, 1 drivers
v0000000001129f60_0 .var "data_write", 0 0;
v000000000112a1e0_0 .var "data_writedata", 31 0;
v0000000001099930_0 .var "in_B", 31 0;
v0000000001182e50_0 .net "in_opcode", 5 0, L_0000000001185360; 1 drivers
v00000000011835d0_0 .net "in_pc_in", 31 0, v00000000011294c0_0; 1 drivers
v0000000001183e90_0 .net "in_readreg1", 4 0, L_0000000001186120; 1 drivers
v0000000001183cb0_0 .net "in_readreg2", 4 0, L_0000000001185c20; 1 drivers
v00000000011833f0_0 .var "in_writedata", 31 0;
v0000000001183990_0 .var "in_writereg", 4 0;
v0000000001184070_0 .var "instr_address", 31 0;
v0000000001182d10_0 .net "instr_readdata", 31 0, L_0000000001185180; alias, 1 drivers
v0000000001184570_0 .net "out_ALUCond", 0 0, v0000000001129060_0; 1 drivers
v0000000001184610_0 .net "out_ALUOp", 4 0, v0000000001128f20_0; 1 drivers
v0000000001183d50_0 .net "out_ALURes", 31 0, v0000000001128980_0; 1 drivers
v0000000001183670_0 .net "out_ALUSrc", 0 0, v00000000011291a0_0; 1 drivers
v0000000001183350_0 .net "out_MemRead", 0 0, v00000000011297e0_0; 1 drivers
v0000000001183df0_0 .net "out_MemWrite", 0 0, v00000000011292e0_0; 1 drivers
v0000000001183210_0 .net "out_MemtoReg", 1 0, v0000000001128a20_0; 1 drivers
v00000000011846b0_0 .net "out_PC", 1 0, v0000000001129ba0_0; 1 drivers
v0000000001183710_0 .net "out_RegDst", 1 0, v0000000001128b60_0; 1 drivers
v0000000001183fd0_0 .net "out_RegWrite", 0 0, v0000000001129240_0; 1 drivers
v0000000001182ef0_0 .var "out_pc_out", 31 0;
v0000000001184390_0 .net "out_readdata1", 31 0, v0000000001129600_0; 1 drivers
v0000000001183490_0 .net "out_readdata2", 31 0, v00000000011296a0_0; 1 drivers
v0000000001184250_0 .net "out_shamt", 4 0, v0000000001128de0_0; 1 drivers
v00000000011841b0_0 .net "register_v0", 31 0, L_000000000111b8c0; alias, 1 drivers
v0000000001183f30_0 .net "reset", 0 0, v00000000011868a0_0; 1 drivers
E_0000000001105ac0/0 .event edge, v0000000001128b60_0, v0000000001129420_0, v0000000001129420_0, v0000000001128a20_0;
E_0000000001105ac0/1 .event edge, v0000000001128980_0, v000000000112a000_0, v00000000011288e0_0, v00000000011291a0_0;
E_0000000001105ac0/2 .event edge, v0000000001129420_0, v0000000001129420_0, v00000000011296a0_0;
E_0000000001105ac0 .event/or E_0000000001105ac0/0, E_0000000001105ac0/1, E_0000000001105ac0/2;
E_0000000001105c00/0 .event edge, v00000000011294c0_0, v0000000001128980_0, v00000000011292e0_0, v00000000011297e0_0;
E_0000000001105c00/1 .event edge, v00000000011296a0_0;
E_0000000001105c00 .event/or E_0000000001105c00/0, E_0000000001105c00/1;
L_0000000001186120 .part L_0000000001185180, 21, 5;
L_0000000001185c20 .part L_0000000001185180, 16, 5;
L_0000000001185360 .part L_0000000001185180, 26, 6;
S_000000000112b710 .scope module, "alu" "mips_cpu_alu" 4 121, 5 1 0, S_000000000112b580;
.timescale 0 0;
.port_info 0 /INPUT 32 "A";
.port_info 1 /INPUT 32 "B";
.port_info 2 /INPUT 5 "ALUOp";
.port_info 3 /INPUT 5 "shamt";
.port_info 4 /OUTPUT 1 "ALUCond";
.port_info 5 /OUTPUT 32 "ALURes";
enum000000000100bd00 .enum4 (5)
"ADD" 5'b00000,
"SUB" 5'b00001,
"MUL" 5'b00010,
"DIV" 5'b00011,
"AND" 5'b00100,
"OR" 5'b00101,
"XOR" 5'b00110,
"SLL" 5'b00111,
"SLLV" 5'b01000,
"SRL" 5'b01001,
"SRLV" 5'b01010,
"SRA" 5'b01011,
"SRAV" 5'b01100,
"EQ" 5'b01101,
"LES" 5'b01110,
"LEQ" 5'b01111,
"GRT" 5'b10000,
"GEQ" 5'b10001,
"NEQ" 5'b10010,
"PAS" 5'b10011,
"SLT" 5'b10100,
"SLTU" 5'b10101,
"MULU" 5'b10110,
"DIVU" 5'b10111
;
L_000000000111bc40 .functor BUFZ 5, v0000000001128f20_0, C4<00000>, C4<00000>, C4<00000>;
v000000000112a460_0 .net "A", 31 0, v0000000001129600_0; alias, 1 drivers
v0000000001129060_0 .var "ALUCond", 0 0;
v000000000112a140_0 .net "ALUOp", 4 0, v0000000001128f20_0; alias, 1 drivers
v00000000011285c0_0 .net "ALUOps", 4 0, L_000000000111bc40; 1 drivers
v0000000001128980_0 .var/s "ALURes", 31 0;
v0000000001128c00_0 .net "B", 31 0, v0000000001099930_0; 1 drivers
v0000000001128660_0 .net "shamt", 4 0, v0000000001128de0_0; alias, 1 drivers
E_0000000001107a80 .event edge, v00000000011285c0_0, v000000000112a460_0, v0000000001128c00_0, v0000000001128660_0;
S_00000000010c9390 .scope module, "control" "mips_cpu_control" 4 90, 6 1 0, S_000000000112b580;
.timescale 0 0;
.port_info 0 /INPUT 32 "Instr";
.port_info 1 /INPUT 1 "ALUCond";
.port_info 2 /OUTPUT 2 "CtrlRegDst";
.port_info 3 /OUTPUT 2 "CtrlPC";
.port_info 4 /OUTPUT 1 "CtrlMemRead";
.port_info 5 /OUTPUT 2 "CtrlMemtoReg";
.port_info 6 /OUTPUT 5 "CtrlALUOp";
.port_info 7 /OUTPUT 5 "Ctrlshamt";
.port_info 8 /OUTPUT 1 "CtrlMemWrite";
.port_info 9 /OUTPUT 1 "CtrlALUSrc";
.port_info 10 /OUTPUT 1 "CtrlRegWrite";
enum0000000001009270 .enum4 (5)
"BLTZ" 5'b00000,
"BGEZ" 5'b00001,
"BLTZAL" 5'b10000,
"BGEZAL" 5'b10001
;
enum0000000001009730 .enum4 (6)
"SPECIAL" 6'b000000,
"REGIMM" 6'b000001,
"J" 6'b000010,
"JAL" 6'b000011,
"BEQ" 6'b000100,
"BNE" 6'b000101,
"BLEZ" 6'b000110,
"BGTZ" 6'b000111,
"ADDI" 6'b001000,
"ADDIU" 6'b001001,
"SLTI" 6'b001010,
"SLTIU" 6'b001011,
"ANDI" 6'b001100,
"ORI" 6'b001101,
"XORI" 6'b001110,
"LUI" 6'b001111,
"LB" 6'b100000,
"LH" 6'b100001,
"LWL" 6'b100010,
"LW" 6'b100011,
"LBU" 6'b100100,
"LHU" 6'b100101,
"LWR" 6'b100110,
"SB" 6'b101000,
"SH" 6'b101001,
"SW" 6'b101011
;
enum000000000100b7f0 .enum4 (6)
"SLL" 6'b000000,
"SRL" 6'b000010,
"SRA" 6'b000011,
"SLLV" 6'b000100,
"SRLV" 6'b000110,
"SRAV" 6'b000111,
"JR" 6'b001000,
"JALR" 6'b001001,
"MTHI" 6'b010001,
"MTLO" 6'b010011,
"MULT" 6'b011000,
"MULTU" 6'b011001,
"DIV" 6'b011010,
"DIVU" 6'b011011,
"ADDU" 6'b100001,
"SUBU" 6'b100011,
"AND" 6'b100100,
"OR" 6'b100101,
"XOR" 6'b100110,
"SLT" 6'b101010,
"SLTU" 6'b101011
;
v0000000001129100_0 .net "ALUCond", 0 0, v0000000001129060_0; alias, 1 drivers
v0000000001128f20_0 .var "CtrlALUOp", 4 0;
v00000000011291a0_0 .var "CtrlALUSrc", 0 0;
v00000000011297e0_0 .var "CtrlMemRead", 0 0;
v00000000011292e0_0 .var "CtrlMemWrite", 0 0;
v0000000001128a20_0 .var "CtrlMemtoReg", 1 0;
v0000000001129ba0_0 .var "CtrlPC", 1 0;
v0000000001128b60_0 .var "CtrlRegDst", 1 0;
v0000000001129240_0 .var "CtrlRegWrite", 0 0;
v0000000001128de0_0 .var "Ctrlshamt", 4 0;
v0000000001129420_0 .net "Instr", 31 0, L_0000000001185180; alias, 1 drivers
v0000000001128700_0 .net "funct", 5 0, L_0000000001185f40; 1 drivers
v0000000001128e80_0 .net "op", 5 0, L_0000000001185cc0; 1 drivers
v0000000001128ac0_0 .net "rt", 4 0, L_0000000001185400; 1 drivers
E_0000000001106ec0/0 .event edge, v0000000001128e80_0, v0000000001128700_0, v0000000001129060_0, v0000000001128ac0_0;
E_0000000001106ec0/1 .event edge, v0000000001129420_0;
E_0000000001106ec0 .event/or E_0000000001106ec0/0, E_0000000001106ec0/1;
L_0000000001185cc0 .part L_0000000001185180, 26, 6;
L_0000000001185f40 .part L_0000000001185180, 0, 6;
L_0000000001185400 .part L_0000000001185180, 16, 5;
S_00000000010c9520 .scope module, "pc" "pc" 4 79, 7 1 0, S_000000000112b580;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 2 "pc_ctrl";
.port_info 3 /INPUT 32 "pc_in";
.port_info 4 /INPUT 5 "rs";
.port_info 5 /OUTPUT 32 "pc_out";
.port_info 6 /OUTPUT 1 "active";
v0000000001129380_0 .var "active", 0 0;
v00000000011287a0_0 .net "clk", 0 0, v0000000001184b40_0; alias, 1 drivers
v0000000001128840_0 .net "pc_ctrl", 1 0, v0000000001129ba0_0; alias, 1 drivers
v0000000001129920_0 .var "pc_curr", 31 0;
v00000000011288e0_0 .net "pc_in", 31 0, v0000000001182ef0_0; 1 drivers
v00000000011294c0_0 .var "pc_out", 31 0;
o000000000112d1d8 .functor BUFZ 5, C4<zzzzz>; HiZ drive
v000000000112a320_0 .net "rs", 4 0, o000000000112d1d8; 0 drivers
v0000000001128fc0_0 .net "rst", 0 0, v00000000011868a0_0; alias, 1 drivers
E_0000000001107bc0 .event posedge, v00000000011287a0_0;
S_00000000010c96b0 .scope module, "regfile" "mips_cpu_regfile" 4 106, 8 1 0, S_000000000112b580;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 5 "readreg1";
.port_info 2 /INPUT 5 "readreg2";
.port_info 3 /INPUT 5 "writereg";
.port_info 4 /INPUT 32 "writedata";
.port_info 5 /INPUT 1 "regwrite";
.port_info 6 /INPUT 6 "opcode";
.port_info 7 /OUTPUT 32 "readdata1";
.port_info 8 /OUTPUT 32 "readdata2";
.port_info 9 /OUTPUT 32 "regv0";
v0000000001129560_2 .array/port v0000000001129560, 2;
L_000000000111b8c0 .functor BUFZ 32, v0000000001129560_2, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
v0000000001129740_0 .net "clk", 0 0, v0000000001184b40_0; alias, 1 drivers
v0000000001129560 .array "memory", 0 31, 31 0;
v0000000001128d40_0 .net "opcode", 5 0, L_0000000001185360; alias, 1 drivers
v0000000001129600_0 .var "readdata1", 31 0;
v00000000011296a0_0 .var "readdata2", 31 0;
v00000000011299c0_0 .net "readreg1", 4 0, L_0000000001186120; alias, 1 drivers
v0000000001129880_0 .net "readreg2", 4 0, L_0000000001185c20; alias, 1 drivers
v000000000112a0a0_0 .net "regv0", 31 0, L_000000000111b8c0; alias, 1 drivers
v0000000001129a60_0 .net "regwrite", 0 0, v0000000001129240_0; alias, 1 drivers
v0000000001129b00_0 .net "writedata", 31 0, v00000000011833f0_0; 1 drivers
v0000000001129c40_0 .net "writereg", 4 0, v0000000001183990_0; 1 drivers
E_0000000001107b80 .event negedge, v00000000011287a0_0;
v0000000001129560_0 .array/port v0000000001129560, 0;
v0000000001129560_1 .array/port v0000000001129560, 1;
E_0000000001107d00/0 .event edge, v00000000011299c0_0, v0000000001129560_0, v0000000001129560_1, v0000000001129560_2;
v0000000001129560_3 .array/port v0000000001129560, 3;
v0000000001129560_4 .array/port v0000000001129560, 4;
v0000000001129560_5 .array/port v0000000001129560, 5;
v0000000001129560_6 .array/port v0000000001129560, 6;
E_0000000001107d00/1 .event edge, v0000000001129560_3, v0000000001129560_4, v0000000001129560_5, v0000000001129560_6;
v0000000001129560_7 .array/port v0000000001129560, 7;
v0000000001129560_8 .array/port v0000000001129560, 8;
v0000000001129560_9 .array/port v0000000001129560, 9;
v0000000001129560_10 .array/port v0000000001129560, 10;
E_0000000001107d00/2 .event edge, v0000000001129560_7, v0000000001129560_8, v0000000001129560_9, v0000000001129560_10;
v0000000001129560_11 .array/port v0000000001129560, 11;
v0000000001129560_12 .array/port v0000000001129560, 12;
v0000000001129560_13 .array/port v0000000001129560, 13;
v0000000001129560_14 .array/port v0000000001129560, 14;
E_0000000001107d00/3 .event edge, v0000000001129560_11, v0000000001129560_12, v0000000001129560_13, v0000000001129560_14;
v0000000001129560_15 .array/port v0000000001129560, 15;
v0000000001129560_16 .array/port v0000000001129560, 16;
v0000000001129560_17 .array/port v0000000001129560, 17;
v0000000001129560_18 .array/port v0000000001129560, 18;
E_0000000001107d00/4 .event edge, v0000000001129560_15, v0000000001129560_16, v0000000001129560_17, v0000000001129560_18;
v0000000001129560_19 .array/port v0000000001129560, 19;
v0000000001129560_20 .array/port v0000000001129560, 20;
v0000000001129560_21 .array/port v0000000001129560, 21;
v0000000001129560_22 .array/port v0000000001129560, 22;
E_0000000001107d00/5 .event edge, v0000000001129560_19, v0000000001129560_20, v0000000001129560_21, v0000000001129560_22;
v0000000001129560_23 .array/port v0000000001129560, 23;
v0000000001129560_24 .array/port v0000000001129560, 24;
v0000000001129560_25 .array/port v0000000001129560, 25;
v0000000001129560_26 .array/port v0000000001129560, 26;
E_0000000001107d00/6 .event edge, v0000000001129560_23, v0000000001129560_24, v0000000001129560_25, v0000000001129560_26;
v0000000001129560_27 .array/port v0000000001129560, 27;
v0000000001129560_28 .array/port v0000000001129560, 28;
v0000000001129560_29 .array/port v0000000001129560, 29;
v0000000001129560_30 .array/port v0000000001129560, 30;
E_0000000001107d00/7 .event edge, v0000000001129560_27, v0000000001129560_28, v0000000001129560_29, v0000000001129560_30;
v0000000001129560_31 .array/port v0000000001129560, 31;
E_0000000001107d00/8 .event edge, v0000000001129560_31, v0000000001129880_0;
E_0000000001107d00 .event/or E_0000000001107d00/0, E_0000000001107d00/1, E_0000000001107d00/2, E_0000000001107d00/3, E_0000000001107d00/4, E_0000000001107d00/5, E_0000000001107d00/6, E_0000000001107d00/7, E_0000000001107d00/8;
S_00000000010b91d0 .scope begin, "$unm_blk_121" "$unm_blk_121" 8 16, 8 16 0, S_00000000010c96b0;
.timescale 0 0;
v0000000001128ca0_0 .var/i "i", 31 0;
S_00000000010b9470 .scope module, "ramInst" "mips_cpu_memory" 3 9, 9 1 0, S_000000000112a580;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 32 "data_address";
.port_info 2 /INPUT 1 "data_write";
.port_info 3 /INPUT 1 "data_read";
.port_info 4 /INPUT 32 "data_writedata";
.port_info 5 /OUTPUT 32 "data_readdata";
.port_info 6 /INPUT 32 "instr_address";
.port_info 7 /OUTPUT 32 "instr_readdata";
P_0000000001107d80 .param/str "RAM_INIT_FILE" 0 9 16, "inputs/ori.txt";
L_000000000111baf0 .functor AND 1, L_00000000011852c0, L_0000000001185860, C4<1>, C4<1>;
v0000000001182db0_0 .net *"_ivl_0", 31 0, L_0000000001184dc0; 1 drivers
L_0000000001187ba8 .functor BUFT 1, C4<10111111110000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000000001184110_0 .net/2u *"_ivl_12", 31 0, L_0000000001187ba8; 1 drivers
v00000000011847f0_0 .net *"_ivl_14", 0 0, L_00000000011852c0; 1 drivers
L_0000000001187bf0 .functor BUFT 1, C4<10111111110000000000000001000000>, C4<0>, C4<0>, C4<0>;
v0000000001184750_0 .net/2u *"_ivl_16", 31 0, L_0000000001187bf0; 1 drivers
v00000000011837b0_0 .net *"_ivl_18", 0 0, L_0000000001185860; 1 drivers
v0000000001184930_0 .net *"_ivl_2", 31 0, L_0000000001186940; 1 drivers
v0000000001184890_0 .net *"_ivl_21", 0 0, L_000000000111baf0; 1 drivers
v0000000001182f90_0 .net *"_ivl_22", 31 0, L_0000000001185900; 1 drivers
L_0000000001187c38 .functor BUFT 1, C4<10111111110000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000000001183030_0 .net/2u *"_ivl_24", 31 0, L_0000000001187c38; 1 drivers
v00000000011842f0_0 .net *"_ivl_26", 31 0, L_0000000001186580; 1 drivers
v0000000001184430_0 .net *"_ivl_28", 31 0, L_0000000001185a40; 1 drivers
v00000000011844d0_0 .net *"_ivl_30", 29 0, L_0000000001184e60; 1 drivers
L_0000000001187c80 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v00000000011849d0_0 .net *"_ivl_32", 1 0, L_0000000001187c80; 1 drivers
L_0000000001187cc8 .functor BUFT 1, C4<xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>, C4<0>, C4<0>, C4<0>;
v00000000011830d0_0 .net *"_ivl_34", 31 0, L_0000000001187cc8; 1 drivers
v0000000001182b30_0 .net *"_ivl_4", 29 0, L_00000000011850e0; 1 drivers
L_0000000001187b18 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000000001182bd0_0 .net *"_ivl_6", 1 0, L_0000000001187b18; 1 drivers
L_0000000001187b60 .functor BUFT 1, C4<xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>, C4<0>, C4<0>, C4<0>;
v0000000001183c10_0 .net *"_ivl_8", 31 0, L_0000000001187b60; 1 drivers
v0000000001183850_0 .net "clk", 0 0, v0000000001184b40_0; alias, 1 drivers
v0000000001183170_0 .net "data_address", 31 0, v0000000001129e20_0; alias, 1 drivers
v00000000011832b0 .array "data_memory", 63 0, 31 0;
v00000000011838f0_0 .net "data_read", 0 0, v0000000001129ec0_0; alias, 1 drivers
v0000000001183b70_0 .net "data_readdata", 31 0, L_0000000001184be0; alias, 1 drivers
v0000000001183a30_0 .net "data_write", 0 0, v0000000001129f60_0; alias, 1 drivers
v0000000001183ad0_0 .net "data_writedata", 31 0, v000000000112a1e0_0; alias, 1 drivers
v0000000001185220_0 .net "instr_address", 31 0, v0000000001184070_0; alias, 1 drivers
v0000000001185ea0 .array "instr_memory", 63 0, 31 0;
v0000000001184f00_0 .net "instr_readdata", 31 0, L_0000000001185180; alias, 1 drivers
L_0000000001184dc0 .array/port v00000000011832b0, L_0000000001186940;
L_00000000011850e0 .part v0000000001129e20_0, 2, 30;
L_0000000001186940 .concat [ 30 2 0 0], L_00000000011850e0, L_0000000001187b18;
L_0000000001184be0 .functor MUXZ 32, L_0000000001187b60, L_0000000001184dc0, v0000000001129ec0_0, C4<>;
L_00000000011852c0 .cmp/ge 32, v0000000001184070_0, L_0000000001187ba8;
L_0000000001185860 .cmp/gt 32, L_0000000001187bf0, v0000000001184070_0;
L_0000000001185900 .array/port v0000000001185ea0, L_0000000001185a40;
L_0000000001186580 .arith/sub 32, v0000000001184070_0, L_0000000001187c38;
L_0000000001184e60 .part L_0000000001186580, 2, 30;
L_0000000001185a40 .concat [ 30 2 0 0], L_0000000001184e60, L_0000000001187c80;
L_0000000001185180 .functor MUXZ 32, L_0000000001187cc8, L_0000000001185900, L_000000000111baf0, C4<>;
S_00000000010ae5e0 .scope begin, "$unm_blk_104" "$unm_blk_104" 9 21, 9 21 0, S_00000000010b9470;
.timescale 0 0;
v0000000001182c70_0 .var/i "i", 31 0;
S_0000000001072680 .scope begin, "$ivl_for_loop0" "$ivl_for_loop0" 9 36, 9 36 0, S_00000000010ae5e0;
.timescale 0 0;
v0000000001183530_0 .var/i "j", 31 0;
.scope S_00000000010b9470;
T_0 ;
%fork t_1, S_00000000010ae5e0;
%jmp t_0;
.scope S_00000000010ae5e0;
t_1 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001182c70_0, 0, 32;
T_0.0 ;
%load/vec4 v0000000001182c70_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_0.1, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 4, v0000000001182c70_0;
%store/vec4a v00000000011832b0, 4, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001182c70_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001182c70_0, 0, 32;
%jmp T_0.0;
T_0.1 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001182c70_0, 0, 32;
T_0.2 ;
%load/vec4 v0000000001182c70_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_0.3, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 4, v0000000001182c70_0;
%store/vec4a v0000000001185ea0, 4, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001182c70_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001182c70_0, 0, 32;
%jmp T_0.2;
T_0.3 ;
%vpi_call/w 9 32 "$display", "RAM: Loading RAM contents from %s", P_0000000001107d80 {0 0 0};
%vpi_call/w 9 33 "$readmemh", P_0000000001107d80, v0000000001185ea0 {0 0 0};
%fork t_3, S_0000000001072680;
%jmp t_2;
.scope S_0000000001072680;
t_3 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001183530_0, 0, 32;
T_0.4 ;
%load/vec4 v0000000001183530_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_0.5, 5;
%pushi/vec4 3217031168, 0, 32;
%load/vec4 v0000000001183530_0;
%muli 4, 0, 32;
%add;
%vpi_call/w 9 37 "$display", "byte +%h: %h", S<0,vec4,u32>, &A<v0000000001185ea0, v0000000001183530_0 > {1 0 0};
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001183530_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001183530_0, 0, 32;
%jmp T_0.4;
T_0.5 ;
%end;
.scope S_00000000010ae5e0;
t_2 %join;
%end;
.scope S_00000000010b9470;
t_0 %join;
%end;
.thread T_0;
.scope S_00000000010b9470;
T_1 ;
%wait E_0000000001107bc0;
%load/vec4 v00000000011838f0_0;
%nor/r;
%load/vec4 v0000000001183a30_0;
%and;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0000000001185220_0;
%load/vec4 v0000000001183170_0;
%cmp/ne;
%jmp/0xz T_1.2, 4;
%load/vec4 v0000000001183ad0_0;
%load/vec4 v0000000001183170_0;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v00000000011832b0, 0, 4;
T_1.2 ;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_00000000010c9520;
T_2 ;
%load/vec4 v00000000011288e0_0;
%store/vec4 v00000000011294c0_0, 0, 32;
%end;
.thread T_2;
.scope S_00000000010c9520;
T_3 ;
%wait E_0000000001107bc0;
%load/vec4 v0000000001128fc0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000000001129380_0, 0;
%pushi/vec4 3217031168, 0, 32;
%assign/vec4 v00000000011294c0_0, 0;
%jmp T_3.1;
T_3.0 ;
%load/vec4 v00000000011294c0_0;
%cmpi/ne 0, 0, 32;
%jmp/0xz T_3.2, 4;
%load/vec4 v0000000001129380_0;
%assign/vec4 v0000000001129380_0, 0;
%load/vec4 v0000000001128840_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_3.4, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_3.5, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_3.6, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_3.7, 6;
%jmp T_3.8;
T_3.4 ;
%load/vec4 v00000000011294c0_0;
%assign/vec4 v0000000001129920_0, 0;
%load/vec4 v0000000001129920_0;
%addi 4, 0, 32;
%assign/vec4 v00000000011294c0_0, 0;
%vpi_call/w 7 27 "$display", "New PC from %h to %h", v0000000001129920_0, v00000000011294c0_0 {0 0 0};
%jmp T_3.8;
T_3.5 ;
%load/vec4 v00000000011288e0_0;
%assign/vec4 v00000000011294c0_0, 0;
%jmp T_3.8;
T_3.6 ;
%load/vec4 v00000000011288e0_0;
%assign/vec4 v00000000011294c0_0, 0;
%jmp T_3.8;
T_3.7 ;
%vpi_call/w 7 36 "$display", "JUMP REGISTER" {0 0 0};
%pushi/vec4 0, 0, 32;
%assign/vec4 v00000000011294c0_0, 0;
%jmp T_3.8;
T_3.8 ;
%pop/vec4 1;
%jmp T_3.3;
T_3.2 ;
%load/vec4 v00000000011294c0_0;
%cmpi/e 0, 0, 32;
%jmp/0xz T_3.9, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000000001129380_0, 0;
T_3.9 ;
T_3.3 ;
T_3.1 ;
%jmp T_3;
.thread T_3;
.scope S_00000000010c9390;
T_4 ;
%wait E_0000000001106ec0;
%vpi_call/w 6 86 "$display", "Opcode: %h", v0000000001128e80_0 {0 0 0};
%load/vec4 v0000000001128e80_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 32, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 15, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 11, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.0, 4;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000000001128b60_0, 0, 2;
%vpi_call/w 6 89 "$display", "CTRLREGDST: Rt" {0 0 0};
%jmp T_4.1;
T_4.0 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 9, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.2, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000000001128b60_0, 0, 2;
%vpi_call/w 6 92 "$display", "CTRLREGDST: Rd" {0 0 0};
%jmp T_4.3;
T_4.2 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 3, 0, 6;
%jmp/0xz T_4.4, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000000001128b60_0, 0, 2;
%vpi_call/w 6 95 "$display", "CTRLREGDST: Link" {0 0 0};
%jmp T_4.5;
T_4.4 ;
%pushi/vec4 1, 1, 2;
%store/vec4 v0000000001128b60_0, 0, 2;
%vpi_call/w 6 96 "$display", "xxxxxxxxxxxxxx" {0 0 0};
T_4.5 ;
T_4.3 ;
T_4.1 ;
%load/vec4 v0000000001129100_0;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 5, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 1, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 17, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 0, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 16, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.6, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000000001129ba0_0, 0, 2;
%jmp T_4.7;
T_4.6 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 2, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 3, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.8, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000000001129ba0_0, 0, 2;
%jmp T_4.9;
T_4.8 ;
%load/vec4 v0000000001128700_0;
%cmpi/e 8, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128700_0;
%cmpi/e 9, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.10, 4;
%pushi/vec4 3, 0, 2;
%store/vec4 v0000000001129ba0_0, 0, 2;
%jmp T_4.11;
T_4.10 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000000001129ba0_0, 0, 2;
T_4.11 ;
T_4.9 ;
T_4.7 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 32, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.12, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000000011297e0_0, 0, 1;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000000001128a20_0, 0, 2;
%vpi_call/w 6 112 "$display", "Memory read enabled" {0 0 0};
%jmp T_4.13;
T_4.12 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 11, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 17, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 19, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.14, 9;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000000011297e0_0, 0, 1;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000000001128a20_0, 0, 2;
%vpi_call/w 6 116 "$display", "Memory read disabled" {0 0 0};
%jmp T_4.15;
T_4.14 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 3, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 9, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.16, 9;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000000001128a20_0, 0, 2;
%jmp T_4.17;
T_4.16 ;
%pushi/vec4 1, 1, 1;
%store/vec4 v00000000011297e0_0, 0, 1;
T_4.17 ;
T_4.15 ;
T_4.13 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.18, 9;
%pushi/vec4 0, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%vpi_call/w 6 124 "$display", "ALU OP = 0 (ADDU/ADDIU)" {0 0 0};
%jmp T_4.19;
T_4.18 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 12, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.20, 9;
%pushi/vec4 4, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.21;
T_4.20 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 4, 0, 6;
%jmp/0xz T_4.22, 4;
%pushi/vec4 13, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.23;
T_4.22 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 1, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 17, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.24, 8;
%pushi/vec4 17, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.25;
T_4.24 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 7, 0, 6;
%jmp/0xz T_4.26, 4;
%pushi/vec4 16, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.27;
T_4.26 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 6, 0, 6;
%jmp/0xz T_4.28, 4;
%pushi/vec4 15, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.29;
T_4.28 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 0, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 16, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.30, 8;
%pushi/vec4 14, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.31;
T_4.30 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 5, 0, 6;
%jmp/0xz T_4.32, 4;
%pushi/vec4 18, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.33;
T_4.32 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.34, 8;
%pushi/vec4 3, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.35;
T_4.34 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.36, 8;
%pushi/vec4 23, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.37;
T_4.36 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 32, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 40, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 41, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 43, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.38, 4;
%pushi/vec4 0, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.39;
T_4.38 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 15, 0, 6;
%jmp/0xz T_4.40, 4;
%pushi/vec4 7, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.41;
T_4.40 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 17, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 19, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.42, 8;
%pushi/vec4 19, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.43;
T_4.42 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.44, 8;
%pushi/vec4 2, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.45;
T_4.44 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.46, 8;
%pushi/vec4 22, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.47;
T_4.46 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 13, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.48, 9;
%pushi/vec4 5, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.49;
T_4.48 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.50, 8;
%pushi/vec4 7, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.51;
T_4.50 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.52, 8;
%pushi/vec4 8, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.53;
T_4.52 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.54, 8;
%pushi/vec4 11, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.55;
T_4.54 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.56, 8;
%pushi/vec4 12, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.57;
T_4.56 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.58, 8;
%pushi/vec4 9, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.59;
T_4.58 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.60, 8;
%pushi/vec4 10, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.61;
T_4.60 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 10, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.62, 9;
%pushi/vec4 20, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.63;
T_4.62 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 11, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.64, 9;
%pushi/vec4 21, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.65;
T_4.64 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.66, 8;
%pushi/vec4 1, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%jmp T_4.67;
T_4.66 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 14, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.68, 9;
%pushi/vec4 6, 0, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
%vpi_call/w 6 175 "$display", "ALU Op = 6 (XOR)" {0 0 0};
%jmp T_4.69;
T_4.68 ;
%pushi/vec4 31, 31, 5;
%store/vec4 v0000000001128f20_0, 0, 5;
T_4.69 ;
T_4.67 ;
T_4.65 ;
T_4.63 ;
T_4.61 ;
T_4.59 ;
T_4.57 ;
T_4.55 ;
T_4.53 ;
T_4.51 ;
T_4.49 ;
T_4.47 ;
T_4.45 ;
T_4.43 ;
T_4.41 ;
T_4.39 ;
T_4.37 ;
T_4.35 ;
T_4.33 ;
T_4.31 ;
T_4.29 ;
T_4.27 ;
T_4.25 ;
T_4.23 ;
T_4.21 ;
T_4.19 ;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.70, 8;
%load/vec4 v0000000001129420_0;
%parti/s 5, 6, 4;
%store/vec4 v0000000001128de0_0, 0, 5;
%jmp T_4.71;
T_4.70 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 15, 0, 6;
%jmp/0xz T_4.72, 4;
%pushi/vec4 16, 0, 5;
%store/vec4 v0000000001128de0_0, 0, 5;
%jmp T_4.73;
T_4.72 ;
%pushi/vec4 31, 31, 5;
%store/vec4 v0000000001128de0_0, 0, 5;
T_4.73 ;
T_4.71 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 40, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 41, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 43, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.74, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000000011292e0_0, 0, 1;
%jmp T_4.75;
T_4.74 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000000011292e0_0, 0, 1;
T_4.75 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 15, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 11, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 32, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 40, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 41, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 43, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.76, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000000011291a0_0, 0, 1;
%jmp T_4.77;
T_4.76 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 4, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 7, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 6, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 5, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 1, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 17, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 0, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128ac0_0;
%pushi/vec4 16, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%flag_or 8, 9;
%jmp/0xz T_4.78, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000000011291a0_0, 0, 1;
%jmp T_4.79;
T_4.78 ;
%pushi/vec4 1, 1, 1;
%store/vec4 v00000000011291a0_0, 0, 1;
T_4.79 ;
T_4.77 ;
%load/vec4 v0000000001128e80_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 32, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 15, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001128e80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001128700_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001128700_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.80, 9;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129240_0, 0, 1;
%jmp T_4.81;
T_4.80 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129240_0, 0, 1;
T_4.81 ;
%jmp T_4;
.thread T_4, $push;
.scope S_00000000010c96b0;
T_5 ;
%fork t_5, S_00000000010b91d0;
%jmp t_4;
.scope S_00000000010b91d0;
t_5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001128ca0_0, 0, 32;
T_5.0 ;
%load/vec4 v0000000001128ca0_0;
%cmpi/s 32, 0, 32;
%jmp/0xz T_5.1, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 4, v0000000001128ca0_0;
%store/vec4a v0000000001129560, 4, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001128ca0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001128ca0_0, 0, 32;
%jmp T_5.0;
T_5.1 ;
%end;
.scope S_00000000010c96b0;
t_4 %join;
%end;
.thread T_5;
.scope S_00000000010c96b0;
T_6 ;
Ewait_0 .event/or E_0000000001107d00, E_0x0;
%wait Ewait_0;
%load/vec4 v00000000011299c0_0;
%pad/u 7;
%ix/vec4 4;
%load/vec4a v0000000001129560, 4;
%store/vec4 v0000000001129600_0, 0, 32;
%load/vec4 v0000000001129880_0;
%pad/u 7;
%ix/vec4 4;
%load/vec4a v0000000001129560, 4;
%store/vec4 v00000000011296a0_0, 0, 32;
%jmp T_6;
.thread T_6, $push;
.scope S_00000000010c96b0;
T_7 ;
%wait E_0000000001107b80;
%load/vec4 v0000000001129c40_0;
%cmpi/e 0, 0, 5;
%jmp/0xz T_7.0, 4;
%jmp T_7.1;
T_7.0 ;
%load/vec4 v0000000001129a60_0;
%flag_set/vec4 8;
%jmp/0xz T_7.2, 8;
%load/vec4 v0000000001128d40_0;
%dup/vec4;
%pushi/vec4 32, 0, 6;
%cmp/u;
%jmp/1 T_7.4, 6;
%dup/vec4;
%pushi/vec4 36, 0, 6;
%cmp/u;
%jmp/1 T_7.5, 6;
%dup/vec4;
%pushi/vec4 33, 0, 6;
%cmp/u;
%jmp/1 T_7.6, 6;
%dup/vec4;
%pushi/vec4 37, 0, 6;
%cmp/u;
%jmp/1 T_7.7, 6;
%dup/vec4;
%pushi/vec4 34, 0, 6;
%cmp/u;
%jmp/1 T_7.8, 6;
%dup/vec4;
%pushi/vec4 38, 0, 6;
%cmp/u;
%jmp/1 T_7.9, 6;
%load/vec4 v0000000001129b00_0;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.11;
T_7.4 ;
%load/vec4 v0000000001129600_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.12, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.13, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.14, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.15, 6;
%jmp T_7.16;
T_7.12 ;
%load/vec4 v0000000001129b00_0;
%parti/s 1, 7, 4;
%replicate 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.16;
T_7.13 ;
%load/vec4 v0000000001129b00_0;
%parti/s 1, 15, 5;
%replicate 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 8, 5;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.16;
T_7.14 ;
%load/vec4 v0000000001129b00_0;
%parti/s 1, 23, 6;
%replicate 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.16;
T_7.15 ;
%load/vec4 v0000000001129b00_0;
%parti/s 1, 31, 6;
%replicate 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 24, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.16;
T_7.16 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.5 ;
%load/vec4 v0000000001129600_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.17, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.18, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.19, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.20, 6;
%jmp T_7.21;
T_7.17 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.21;
T_7.18 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 8, 5;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.21;
T_7.19 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.21;
T_7.20 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 24, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.21;
T_7.21 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.6 ;
%load/vec4 v0000000001129600_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.22, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.23, 6;
%jmp T_7.24;
T_7.22 ;
%load/vec4 v0000000001129b00_0;
%parti/s 1, 15, 5;
%replicate 16;
%load/vec4 v0000000001129b00_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.24;
T_7.23 ;
%load/vec4 v0000000001129b00_0;
%parti/s 1, 31, 6;
%replicate 16;
%load/vec4 v0000000001129b00_0;
%parti/s 16, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.24;
T_7.24 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.7 ;
%load/vec4 v0000000001129600_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.25, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.26, 6;
%jmp T_7.27;
T_7.25 ;
%pushi/vec4 0, 0, 16;
%load/vec4 v0000000001129b00_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.27;
T_7.26 ;
%pushi/vec4 0, 0, 16;
%load/vec4 v0000000001129b00_0;
%parti/s 16, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.27;
T_7.27 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.8 ;
%load/vec4 v0000000001129600_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.28, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.29, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.30, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.31, 6;
%jmp T_7.32;
T_7.28 ;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 0, 2;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 24, 0; part off
%ix/load 5, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 4, 5;
%jmp T_7.32;
T_7.29 ;
%load/vec4 v0000000001129b00_0;
%parti/s 16, 0, 2;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 16, 0; part off
%ix/load 5, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 4, 5;
%jmp T_7.32;
T_7.30 ;
%load/vec4 v0000000001129b00_0;
%parti/s 24, 0, 2;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 8, 0; part off
%ix/load 5, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 4, 5;
%jmp T_7.32;
T_7.31 ;
%load/vec4 v0000000001129b00_0;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.32;
T_7.32 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.9 ;
%load/vec4 v0000000001129600_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.33, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.34, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.35, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.36, 6;
%jmp T_7.37;
T_7.33 ;
%load/vec4 v0000000001129b00_0;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.37;
T_7.34 ;
%load/vec4 v0000000001129b00_0;
%parti/s 24, 8, 5;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.37;
T_7.35 ;
%load/vec4 v0000000001129b00_0;
%parti/s 16, 16, 6;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.37;
T_7.36 ;
%load/vec4 v0000000001129b00_0;
%parti/s 8, 24, 6;
%load/vec4 v0000000001129c40_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001129560, 0, 4;
%jmp T_7.37;
T_7.37 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.11 ;
%pop/vec4 1;
T_7.2 ;
T_7.1 ;
%jmp T_7;
.thread T_7;
.scope S_000000000112b710;
T_8 ;
Ewait_1 .event/or E_0000000001107a80, E_0x0;
%wait Ewait_1;
%load/vec4 v00000000011285c0_0;
%dup/vec4;
%pushi/vec4 0, 0, 5;
%cmp/u;
%jmp/1 T_8.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 5;
%cmp/u;
%jmp/1 T_8.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 5;
%cmp/u;
%jmp/1 T_8.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 5;
%cmp/u;
%jmp/1 T_8.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 5;
%cmp/u;
%jmp/1 T_8.4, 6;
%dup/vec4;
%pushi/vec4 5, 0, 5;
%cmp/u;
%jmp/1 T_8.5, 6;
%dup/vec4;
%pushi/vec4 6, 0, 5;
%cmp/u;
%jmp/1 T_8.6, 6;
%dup/vec4;
%pushi/vec4 7, 0, 5;
%cmp/u;
%jmp/1 T_8.7, 6;
%dup/vec4;
%pushi/vec4 8, 0, 5;
%cmp/u;
%jmp/1 T_8.8, 6;
%dup/vec4;
%pushi/vec4 9, 0, 5;
%cmp/u;
%jmp/1 T_8.9, 6;
%dup/vec4;
%pushi/vec4 10, 0, 5;
%cmp/u;
%jmp/1 T_8.10, 6;
%dup/vec4;
%pushi/vec4 11, 0, 5;
%cmp/u;
%jmp/1 T_8.11, 6;
%dup/vec4;
%pushi/vec4 12, 0, 5;
%cmp/u;
%jmp/1 T_8.12, 6;
%dup/vec4;
%pushi/vec4 13, 0, 5;
%cmp/u;
%jmp/1 T_8.13, 6;
%dup/vec4;
%pushi/vec4 14, 0, 5;
%cmp/u;
%jmp/1 T_8.14, 6;
%dup/vec4;
%pushi/vec4 15, 0, 5;
%cmp/u;
%jmp/1 T_8.15, 6;
%dup/vec4;
%pushi/vec4 16, 0, 5;
%cmp/u;
%jmp/1 T_8.16, 6;
%dup/vec4;
%pushi/vec4 17, 0, 5;
%cmp/u;
%jmp/1 T_8.17, 6;
%dup/vec4;
%pushi/vec4 18, 0, 5;
%cmp/u;
%jmp/1 T_8.18, 6;
%dup/vec4;
%pushi/vec4 19, 0, 5;
%cmp/u;
%jmp/1 T_8.19, 6;
%dup/vec4;
%pushi/vec4 20, 0, 5;
%cmp/u;
%jmp/1 T_8.20, 6;
%dup/vec4;
%pushi/vec4 21, 0, 5;
%cmp/u;
%jmp/1 T_8.21, 6;
%dup/vec4;
%pushi/vec4 22, 0, 5;
%cmp/u;
%jmp/1 T_8.22, 6;
%dup/vec4;
%pushi/vec4 23, 0, 5;
%cmp/u;
%jmp/1 T_8.23, 6;
%jmp T_8.24;
T_8.0 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%add;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.1 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%sub;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.2 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%mul;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.3 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%div/s;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.4 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%and;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.5 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%or;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.6 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%xor;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.7 ;
%load/vec4 v0000000001128c00_0;
%ix/getv 4, v0000000001128660_0;
%shiftl 4;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.8 ;
%load/vec4 v0000000001128c00_0;
%ix/getv 4, v000000000112a460_0;
%shiftl 4;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.9 ;
%load/vec4 v0000000001128c00_0;
%ix/getv 4, v0000000001128660_0;
%shiftr 4;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.10 ;
%load/vec4 v0000000001128c00_0;
%ix/getv 4, v000000000112a460_0;
%shiftr 4;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.11 ;
%load/vec4 v0000000001128c00_0;
%ix/getv 4, v0000000001128660_0;
%shiftr 4;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.12 ;
%load/vec4 v0000000001128c00_0;
%ix/getv 4, v000000000112a460_0;
%shiftr 4;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.13 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%cmp/e;
%jmp/0xz T_8.25, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
%jmp T_8.26;
T_8.25 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
T_8.26 ;
%jmp T_8.24;
T_8.14 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%cmp/s;
%jmp/0xz T_8.27, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
%jmp T_8.28;
T_8.27 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
T_8.28 ;
%jmp T_8.24;
T_8.15 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%cmp/s;
%flag_or 5, 4;
%jmp/0xz T_8.29, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
%jmp T_8.30;
T_8.29 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
T_8.30 ;
%jmp T_8.24;
T_8.16 ;
%load/vec4 v0000000001128c00_0;
%load/vec4 v000000000112a460_0;
%cmp/s;
%jmp/0xz T_8.31, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
%jmp T_8.32;
T_8.31 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
T_8.32 ;
%jmp T_8.24;
T_8.17 ;
%load/vec4 v0000000001128c00_0;
%load/vec4 v000000000112a460_0;
%cmp/s;
%flag_or 5, 4;
%jmp/0xz T_8.33, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
%jmp T_8.34;
T_8.33 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
T_8.34 ;
%jmp T_8.24;
T_8.18 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%cmp/ne;
%jmp/0xz T_8.35, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
%jmp T_8.36;
T_8.35 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001129060_0, 0, 1;
T_8.36 ;
%jmp T_8.24;
T_8.19 ;
%load/vec4 v000000000112a460_0;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.20 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%cmp/s;
%jmp/0xz T_8.37, 5;
%pushi/vec4 1, 0, 32;
%store/vec4 v0000000001128980_0, 0, 32;
T_8.37 ;
%jmp T_8.24;
T_8.21 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%cmp/u;
%jmp/0xz T_8.39, 5;
%pushi/vec4 1, 0, 32;
%store/vec4 v0000000001128980_0, 0, 32;
T_8.39 ;
%jmp T_8.24;
T_8.22 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%mul;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.23 ;
%load/vec4 v000000000112a460_0;
%load/vec4 v0000000001128c00_0;
%div;
%store/vec4 v0000000001128980_0, 0, 32;
%jmp T_8.24;
T_8.24 ;
%pop/vec4 1;
%jmp T_8;
.thread T_8, $push;
.scope S_000000000112b580;
T_9 ;
%pushi/vec4 3217031168, 0, 32;
%store/vec4 v0000000001182ef0_0, 0, 32;
%end;
.thread T_9, $init;
.scope S_000000000112b580;
T_10 ;
Ewait_2 .event/or E_0000000001105c00, E_0x0;
%wait Ewait_2;
%load/vec4 v00000000011835d0_0;
%store/vec4 v0000000001184070_0, 0, 32;
%load/vec4 v0000000001183d50_0;
%store/vec4 v0000000001129e20_0, 0, 32;
%load/vec4 v0000000001183df0_0;
%store/vec4 v0000000001129f60_0, 0, 1;
%load/vec4 v0000000001183350_0;
%store/vec4 v0000000001129ec0_0, 0, 1;
%load/vec4 v0000000001183490_0;
%store/vec4 v000000000112a1e0_0, 0, 32;
%jmp T_10;
.thread T_10, $push;
.scope S_000000000112b580;
T_11 ;
Ewait_3 .event/or E_0000000001105ac0, E_0x0;
%wait Ewait_3;
%load/vec4 v0000000001183710_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_11.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_11.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_11.2, 6;
%jmp T_11.3;
T_11.0 ;
%load/vec4 v0000000001182d10_0;
%parti/s 5, 16, 6;
%store/vec4 v0000000001183990_0, 0, 5;
%jmp T_11.3;
T_11.1 ;
%load/vec4 v0000000001182d10_0;
%parti/s 5, 11, 5;
%store/vec4 v0000000001183990_0, 0, 5;
%jmp T_11.3;
T_11.2 ;
%pushi/vec4 31, 0, 5;
%store/vec4 v0000000001183990_0, 0, 5;
%jmp T_11.3;
T_11.3 ;
%pop/vec4 1;
%load/vec4 v0000000001183210_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_11.4, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_11.5, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_11.6, 6;
%jmp T_11.7;
T_11.4 ;
%load/vec4 v0000000001183d50_0;
%store/vec4 v00000000011833f0_0, 0, 32;
%jmp T_11.7;
T_11.5 ;
%load/vec4 v000000000112a000_0;
%store/vec4 v00000000011833f0_0, 0, 32;
%jmp T_11.7;
T_11.6 ;
%load/vec4 v0000000001182ef0_0;
%addi 8, 0, 32;
%store/vec4 v00000000011833f0_0, 0, 32;
%jmp T_11.7;
T_11.7 ;
%pop/vec4 1;
%load/vec4 v0000000001183670_0;
%dup/vec4;
%pushi/vec4 1, 0, 1;
%cmp/u;
%jmp/1 T_11.8, 6;
%dup/vec4;
%pushi/vec4 0, 0, 1;
%cmp/u;
%jmp/1 T_11.9, 6;
%jmp T_11.10;
T_11.8 ;
%load/vec4 v0000000001182d10_0;
%parti/s 1, 15, 5;
%replicate 16;
%load/vec4 v0000000001182d10_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%store/vec4 v0000000001099930_0, 0, 32;
%jmp T_11.10;
T_11.9 ;
%load/vec4 v0000000001183490_0;
%store/vec4 v0000000001099930_0, 0, 32;
%jmp T_11.10;
T_11.10 ;
%pop/vec4 1;
%jmp T_11;
.thread T_11, $push;
.scope S_000000000112a580;
T_12 ;
%vpi_call/w 3 36 "$dumpfile", "mips_cpu_harvard.vcd" {0 0 0};
%vpi_call/w 3 37 "$dumpvars", 32'sb00000000000000000000000000000000, S_000000000112a580 {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001184b40_0, 0, 1;
%pushi/vec4 100, 0, 32;
T_12.0 %dup/vec4;
%pushi/vec4 0, 0, 32;
%cmp/s;
%jmp/1xz T_12.1, 5;
%jmp/1 T_12.1, 4;
%pushi/vec4 1, 0, 32;
%sub;
%delay 10, 0;
%load/vec4 v0000000001184b40_0;
%nor/r;
%store/vec4 v0000000001184b40_0, 0, 1;
%delay 10, 0;
%load/vec4 v0000000001184b40_0;
%nor/r;
%store/vec4 v0000000001184b40_0, 0, 1;
%jmp T_12.0;
T_12.1 ;
%pop/vec4 1;
%vpi_call/w 3 47 "$fatal", 32'sb00000000000000000000000000000010, "Simulation did not finish within %d cycles.", P_00000000010f3f28 {0 0 0};
%end;
.thread T_12;
.scope S_000000000112a580;
T_13 ;
%vpi_call/w 3 51 "$display", "Initial Reset 0" {0 0 0};
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000000011868a0_0, 0;
%vpi_call/w 3 55 "$display", "Initial Reset 1" {0 0 0};
%wait E_0000000001107bc0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000000011868a0_0, 0;
%vpi_call/w 3 59 "$display", "Initial Reset 0: Start Program" {0 0 0};
%wait E_0000000001107bc0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000000011868a0_0, 0;
%wait E_0000000001107bc0;
%load/vec4 v0000000001184fa0_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_13.0, 4;
%jmp T_13.1;
T_13.0 ;
%vpi_call/w 3 65 "$display", "TB: CPU did not set active=1 after reset." {0 0 0};
T_13.1 ;
T_13.2 ;
%load/vec4 v0000000001184fa0_0;
%flag_set/vec4 8;
%jmp/0xz T_13.3, 8;
%wait E_0000000001107bc0;
%vpi_call/w 3 71 "$display", "Reg File Write data: %d", v00000000011833f0_0 {0 0 0};
%jmp T_13.2;
T_13.3 ;
%wait E_0000000001107bc0;
%vpi_call/w 3 74 "$display", "TB: CPU Halt; active=0" {0 0 0};
%vpi_call/w 3 75 "$display", "Output:" {0 0 0};
%vpi_call/w 3 76 "$display", "%d", v00000000011869e0_0 {0 0 0};
%vpi_call/w 3 77 "$finish" {0 0 0};
%end;
.thread T_13;
# The file index is used to find the file name in the following table.
:file_names 10;
"N/A";
"<interactive>";
"-";
"testbench/mips_cpu_harvard_tb.v";
"rtl/mips_cpu_harvard.v";
"rtl/mips_cpu_alu.v";
"rtl/mips_cpu_control.v";
"rtl/mips_cpu_pc.v";
"rtl/mips_cpu_regfile.v";
"rtl/mips_cpu_memory.v";
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