supleed2/ELEC50010-IAC-CW
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ELEC50010-IAC-CW/exec/mips_cpu_harvard_tb_o
jl7719 3594365a25 Create branch jl7719 
Can test for normal pc incrementing instr
2020-12-11 19:45:13 +09:00

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#! /usr/local/iverilog/bin/vvp
:ivl_version "11.0 (devel)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2009.vpi";
S_00000000010e0110 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_000000000110ada0 .scope module, "mips_cpu_harvard_tb" "mips_cpu_harvard_tb" 3 1;
.timescale 0 0;
P_00000000010d9790 .param/str "RAM_INIT_FILE" 0 3 3, "inputs/o.txt";
P_00000000010d97c8 .param/l "TIMEOUT_CYCLES" 0 3 4, +C4<00000000000000000000000001100100>;
v0000000001165b00_0 .net "active", 0 0, v0000000001108d20_0; 1 drivers
v0000000001166460_0 .var "clk", 0 0;
v0000000001165060_0 .var "clk_enable", 0 0;
v0000000001166820_0 .net "data_address", 31 0, v0000000001109860_0; 1 drivers
v0000000001165ce0_0 .net "data_read", 0 0, v0000000001109900_0; 1 drivers
v0000000001164980_0 .net "data_readdata", 31 0, L_00000000011659c0; 1 drivers
v00000000011666e0_0 .net "data_write", 0 0, v0000000001109a40_0; 1 drivers
v0000000001166280_0 .net "data_writedata", 31 0, v0000000001109c20_0; 1 drivers
v0000000001165f60_0 .net "instr_address", 31 0, v0000000001162ab0_0; 1 drivers
v0000000001165100_0 .net "instr_readdata", 31 0, L_0000000001165600; 1 drivers
v0000000001165560_0 .net "register_v0", 31 0, L_00000000010ee000; 1 drivers
v0000000001166000_0 .var "reset", 0 0;
S_000000000110af30 .scope module, "cpuInst" "mips_cpu_harvard" 3 19, 4 1 0, S_000000000110ada0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "reset";
.port_info 2 /OUTPUT 1 "active";
.port_info 3 /OUTPUT 32 "register_v0";
.port_info 4 /INPUT 1 "clk_enable";
.port_info 5 /OUTPUT 32 "instr_address";
.port_info 6 /INPUT 32 "instr_readdata";
.port_info 7 /OUTPUT 32 "data_address";
.port_info 8 /OUTPUT 1 "data_write";
.port_info 9 /OUTPUT 1 "data_read";
.port_info 10 /OUTPUT 32 "data_writedata";
.port_info 11 /INPUT 32 "data_readdata";
v0000000001109720_0 .net "active", 0 0, v0000000001108d20_0; alias, 1 drivers
v00000000011094a0_0 .net "clk", 0 0, v0000000001166460_0; 1 drivers
v00000000011097c0_0 .net "clk_enable", 0 0, v0000000001165060_0; 1 drivers
v0000000001109860_0 .var "data_address", 31 0;
v0000000001109900_0 .var "data_read", 0 0;
v00000000011099a0_0 .net "data_readdata", 31 0, L_00000000011659c0; alias, 1 drivers
v0000000001109a40_0 .var "data_write", 0 0;
v0000000001109c20_0 .var "data_writedata", 31 0;
v00000000010ce2e0_0 .var "in_B", 31 0;
v0000000001162dd0_0 .net "in_opcode", 5 0, L_0000000001166320; 1 drivers
v0000000001163af0_0 .net "in_pc_in", 31 0, v0000000001109fe0_0; 1 drivers
v0000000001162b50_0 .net "in_readreg1", 4 0, L_0000000001165380; 1 drivers
v0000000001164770_0 .net "in_readreg2", 4 0, L_0000000001165ba0; 1 drivers
v0000000001164310_0 .var "in_writedata", 31 0;
v00000000011641d0_0 .var "in_writereg", 4 0;
v0000000001162ab0_0 .var "instr_address", 31 0;
v0000000001162d30_0 .net "instr_readdata", 31 0, L_0000000001165600; alias, 1 drivers
v0000000001163a50_0 .net "out_ALUCond", 0 0, v000000000110a1c0_0; 1 drivers
v00000000011639b0_0 .net "out_ALUOp", 4 0, v0000000001108b40_0; 1 drivers
v0000000001162bf0_0 .net "out_ALURes", 31 0, v0000000001109ae0_0; 1 drivers
v0000000001164270_0 .net "out_ALUSrc", 0 0, v00000000011090e0_0; 1 drivers
v00000000011643b0_0 .net "out_MemRead", 0 0, v000000000110a4e0_0; 1 drivers
v0000000001162c90_0 .net "out_MemWrite", 0 0, v0000000001109040_0; 1 drivers
v0000000001162e70_0 .net "out_MemtoReg", 1 0, v000000000110a800_0; 1 drivers
v00000000011644f0_0 .net "out_PC", 1 0, v0000000001109cc0_0; 1 drivers
v0000000001162a10_0 .net "out_RegDst", 1 0, v0000000001108960_0; 1 drivers
v0000000001163410_0 .net "out_RegWrite", 0 0, v000000000110a6c0_0; 1 drivers
v0000000001164090_0 .var "out_pc_out", 31 0;
v0000000001162f10_0 .net "out_readdata1", 31 0, v0000000001108f00_0; 1 drivers
v00000000011634b0_0 .net "out_readdata2", 31 0, v000000000110a120_0; 1 drivers
v00000000011630f0_0 .net "out_shamt", 4 0, v0000000001109e00_0; 1 drivers
v0000000001164590_0 .net "register_v0", 31 0, L_00000000010ee000; alias, 1 drivers
v0000000001162fb0_0 .net "reset", 0 0, v0000000001166000_0; 1 drivers
E_00000000010e5c00/0 .event edge, v0000000001108960_0, v0000000001109180_0, v0000000001109180_0, v000000000110a800_0;
E_00000000010e5c00/1 .event edge, v0000000001109ae0_0, v00000000011099a0_0, v0000000001109220_0, v00000000011090e0_0;
E_00000000010e5c00/2 .event edge, v0000000001109180_0, v0000000001109180_0, v000000000110a120_0;
E_00000000010e5c00 .event/or E_00000000010e5c00/0, E_00000000010e5c00/1, E_00000000010e5c00/2;
E_00000000010e61c0/0 .event edge, v0000000001109fe0_0, v0000000001109ae0_0, v0000000001109040_0, v000000000110a4e0_0;
E_00000000010e61c0/1 .event edge, v000000000110a120_0;
E_00000000010e61c0 .event/or E_00000000010e61c0/0, E_00000000010e61c0/1;
L_0000000001165380 .part L_0000000001165600, 21, 5;
L_0000000001165ba0 .part L_0000000001165600, 16, 5;
L_0000000001166320 .part L_0000000001165600, 26, 6;
S_00000000010a5e30 .scope module, "alu" "mips_cpu_alu" 4 121, 5 1 0, S_000000000110af30;
.timescale 0 0;
.port_info 0 /INPUT 32 "A";
.port_info 1 /INPUT 32 "B";
.port_info 2 /INPUT 5 "ALUOp";
.port_info 3 /INPUT 5 "shamt";
.port_info 4 /OUTPUT 1 "ALUCond";
.port_info 5 /OUTPUT 32 "ALURes";
enum0000000000febd00 .enum4 (5)
"ADD" 5'b00000,
"SUB" 5'b00001,
"MUL" 5'b00010,
"DIV" 5'b00011,
"AND" 5'b00100,
"OR" 5'b00101,
"XOR" 5'b00110,
"SLL" 5'b00111,
"SLLV" 5'b01000,
"SRL" 5'b01001,
"SRLV" 5'b01010,
"SRA" 5'b01011,
"SRAV" 5'b01100,
"EQ" 5'b01101,
"LES" 5'b01110,
"LEQ" 5'b01111,
"GRT" 5'b10000,
"GEQ" 5'b10001,
"NEQ" 5'b10010,
"PAS" 5'b10011,
"SLT" 5'b10100,
"SLTU" 5'b10101,
"MULU" 5'b10110,
"DIVU" 5'b10111
;
L_00000000010ee0e0 .functor BUFZ 5, v0000000001108b40_0, C4<00000>, C4<00000>, C4<00000>;
v000000000110a580_0 .net "A", 31 0, v0000000001108f00_0; alias, 1 drivers
v000000000110a1c0_0 .var "ALUCond", 0 0;
v0000000001108aa0_0 .net "ALUOp", 4 0, v0000000001108b40_0; alias, 1 drivers
v0000000001108fa0_0 .net "ALUOps", 4 0, L_00000000010ee0e0; 1 drivers
v0000000001109ae0_0 .var/s "ALURes", 31 0;
v0000000001108be0_0 .net "B", 31 0, v00000000010ce2e0_0; 1 drivers
v000000000110a260_0 .net "shamt", 4 0, v0000000001109e00_0; alias, 1 drivers
E_00000000010e7f00 .event edge, v0000000001108fa0_0, v000000000110a580_0, v0000000001108be0_0, v000000000110a260_0;
S_00000000010a5fc0 .scope module, "control" "mips_cpu_control" 4 90, 6 1 0, S_000000000110af30;
.timescale 0 0;
.port_info 0 /INPUT 32 "Instr";
.port_info 1 /INPUT 1 "ALUCond";
.port_info 2 /OUTPUT 2 "CtrlRegDst";
.port_info 3 /OUTPUT 2 "CtrlPC";
.port_info 4 /OUTPUT 1 "CtrlMemRead";
.port_info 5 /OUTPUT 2 "CtrlMemtoReg";
.port_info 6 /OUTPUT 5 "CtrlALUOp";
.port_info 7 /OUTPUT 5 "Ctrlshamt";
.port_info 8 /OUTPUT 1 "CtrlMemWrite";
.port_info 9 /OUTPUT 1 "CtrlALUSrc";
.port_info 10 /OUTPUT 1 "CtrlRegWrite";
enum0000000000fe9270 .enum4 (6)
"SLL" 6'b000000,
"SRL" 6'b000010,
"SRA" 6'b000011,
"SLLV" 6'b000100,
"SRLV" 6'b000110,
"SRAV" 6'b000111,
"JR" 6'b001000,
"JALR" 6'b001001,
"MTHI" 6'b010001,
"MTLO" 6'b010011,
"MULT" 6'b011000,
"MULTU" 6'b011001,
"DIV" 6'b011010,
"DIVU" 6'b011011,
"ADDU" 6'b100001,
"SUBU" 6'b100011,
"AND" 6'b100100,
"OR" 6'b100101,
"XOR" 6'b100110,
"SLT" 6'b101010,
"SLTU" 6'b101011
;
enum0000000000feb8a0 .enum4 (6)
"SPECIAL" 6'b000000,
"REGIMM" 6'b000001,
"J" 6'b000010,
"JAL" 6'b000011,
"BEQ" 6'b000100,
"BNE" 6'b000101,
"BLEZ" 6'b000110,
"BGTZ" 6'b000111,
"ADDI" 6'b001000,
"ADDIU" 6'b001001,
"SLTI" 6'b001010,
"SLTIU" 6'b001011,
"ANDI" 6'b001100,
"ORI" 6'b001101,
"XORI" 6'b001110,
"LUI" 6'b001111,
"LB" 6'b100000,
"LH" 6'b100001,
"LWL" 6'b100010,
"LW" 6'b100011,
"LBU" 6'b100100,
"LHU" 6'b100101,
"LWR" 6'b100110,
"SB" 6'b101000,
"SH" 6'b101001,
"SW" 6'b101011
;
enum0000000000feb950 .enum4 (5)
"BLTZ" 5'b00000,
"BGEZ" 5'b00001,
"BLTZAL" 5'b10000,
"BGEZAL" 5'b10001
;
v0000000001109680_0 .net "ALUCond", 0 0, v000000000110a1c0_0; alias, 1 drivers
v0000000001108b40_0 .var "CtrlALUOp", 4 0;
v00000000011090e0_0 .var "CtrlALUSrc", 0 0;
v000000000110a4e0_0 .var "CtrlMemRead", 0 0;
v0000000001109040_0 .var "CtrlMemWrite", 0 0;
v000000000110a800_0 .var "CtrlMemtoReg", 1 0;
v0000000001109cc0_0 .var "CtrlPC", 1 0;
v0000000001108960_0 .var "CtrlRegDst", 1 0;
v000000000110a6c0_0 .var "CtrlRegWrite", 0 0;
v0000000001109e00_0 .var "Ctrlshamt", 4 0;
v0000000001109180_0 .net "Instr", 31 0, L_0000000001165600; alias, 1 drivers
v0000000001108c80_0 .net "funct", 5 0, L_0000000001164ac0; 1 drivers
v0000000001109540_0 .net "op", 5 0, L_0000000001166500; 1 drivers
v0000000001109f40_0 .net "rt", 4 0, L_0000000001164a20; 1 drivers
E_00000000010e7040/0 .event edge, v0000000001109540_0, v0000000001108c80_0, v000000000110a1c0_0, v0000000001109f40_0;
E_00000000010e7040/1 .event edge, v0000000001109180_0;
E_00000000010e7040 .event/or E_00000000010e7040/0, E_00000000010e7040/1;
L_0000000001166500 .part L_0000000001165600, 26, 6;
L_0000000001164ac0 .part L_0000000001165600, 0, 6;
L_0000000001164a20 .part L_0000000001165600, 16, 5;
S_00000000010a6150 .scope module, "pc" "pc" 4 79, 7 1 0, S_000000000110af30;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 2 "pc_ctrl";
.port_info 3 /INPUT 32 "pc_in";
.port_info 4 /INPUT 5 "rs";
.port_info 5 /OUTPUT 32 "pc_out";
.port_info 6 /OUTPUT 1 "active";
v0000000001108d20_0 .var "active", 0 0;
v000000000110a620_0 .net "clk", 0 0, v0000000001166460_0; alias, 1 drivers
v0000000001109d60_0 .net "pc_ctrl", 1 0, v0000000001109cc0_0; alias, 1 drivers
v0000000001109ea0_0 .var "pc_curr", 31 0;
v0000000001109220_0 .net "pc_in", 31 0, v0000000001164090_0; 1 drivers
v0000000001109fe0_0 .var "pc_out", 31 0;
o000000000110d018 .functor BUFZ 5, C4<zzzzz>; HiZ drive
v000000000110a080_0 .net "rs", 4 0, o000000000110d018; 0 drivers
v00000000011095e0_0 .net "rst", 0 0, v0000000001166000_0; alias, 1 drivers
E_00000000010e8000 .event posedge, v000000000110a620_0;
S_00000000010991d0 .scope module, "regfile" "mips_cpu_regfile" 4 106, 8 1 0, S_000000000110af30;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 5 "readreg1";
.port_info 2 /INPUT 5 "readreg2";
.port_info 3 /INPUT 5 "writereg";
.port_info 4 /INPUT 32 "writedata";
.port_info 5 /INPUT 1 "regwrite";
.port_info 6 /INPUT 6 "opcode";
.port_info 7 /OUTPUT 32 "readdata1";
.port_info 8 /OUTPUT 32 "readdata2";
.port_info 9 /OUTPUT 32 "regv0";
v0000000001108e60_2 .array/port v0000000001108e60, 2;
L_00000000010ee000 .functor BUFZ 32, v0000000001108e60_2, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
v000000000110a760_0 .net "clk", 0 0, v0000000001166460_0; alias, 1 drivers
v0000000001108e60 .array "memory", 0 31, 31 0;
v0000000001108a00_0 .net "opcode", 5 0, L_0000000001166320; alias, 1 drivers
v0000000001108f00_0 .var "readdata1", 31 0;
v000000000110a120_0 .var "readdata2", 31 0;
v000000000110a440_0 .net "readreg1", 4 0, L_0000000001165380; alias, 1 drivers
v00000000011092c0_0 .net "readreg2", 4 0, L_0000000001165ba0; alias, 1 drivers
v0000000001109360_0 .net "regv0", 31 0, L_00000000010ee000; alias, 1 drivers
v0000000001109400_0 .net "regwrite", 0 0, v000000000110a6c0_0; alias, 1 drivers
v000000000110a300_0 .net "writedata", 31 0, v0000000001164310_0; 1 drivers
v000000000110a3a0_0 .net "writereg", 4 0, v00000000011641d0_0; 1 drivers
E_00000000010e7f80 .event negedge, v000000000110a620_0;
v0000000001108e60_0 .array/port v0000000001108e60, 0;
v0000000001108e60_1 .array/port v0000000001108e60, 1;
E_00000000010e80c0/0 .event edge, v000000000110a440_0, v0000000001108e60_0, v0000000001108e60_1, v0000000001108e60_2;
v0000000001108e60_3 .array/port v0000000001108e60, 3;
v0000000001108e60_4 .array/port v0000000001108e60, 4;
v0000000001108e60_5 .array/port v0000000001108e60, 5;
v0000000001108e60_6 .array/port v0000000001108e60, 6;
E_00000000010e80c0/1 .event edge, v0000000001108e60_3, v0000000001108e60_4, v0000000001108e60_5, v0000000001108e60_6;
v0000000001108e60_7 .array/port v0000000001108e60, 7;
v0000000001108e60_8 .array/port v0000000001108e60, 8;
v0000000001108e60_9 .array/port v0000000001108e60, 9;
v0000000001108e60_10 .array/port v0000000001108e60, 10;
E_00000000010e80c0/2 .event edge, v0000000001108e60_7, v0000000001108e60_8, v0000000001108e60_9, v0000000001108e60_10;
v0000000001108e60_11 .array/port v0000000001108e60, 11;
v0000000001108e60_12 .array/port v0000000001108e60, 12;
v0000000001108e60_13 .array/port v0000000001108e60, 13;
v0000000001108e60_14 .array/port v0000000001108e60, 14;
E_00000000010e80c0/3 .event edge, v0000000001108e60_11, v0000000001108e60_12, v0000000001108e60_13, v0000000001108e60_14;
v0000000001108e60_15 .array/port v0000000001108e60, 15;
v0000000001108e60_16 .array/port v0000000001108e60, 16;
v0000000001108e60_17 .array/port v0000000001108e60, 17;
v0000000001108e60_18 .array/port v0000000001108e60, 18;
E_00000000010e80c0/4 .event edge, v0000000001108e60_15, v0000000001108e60_16, v0000000001108e60_17, v0000000001108e60_18;
v0000000001108e60_19 .array/port v0000000001108e60, 19;
v0000000001108e60_20 .array/port v0000000001108e60, 20;
v0000000001108e60_21 .array/port v0000000001108e60, 21;
v0000000001108e60_22 .array/port v0000000001108e60, 22;
E_00000000010e80c0/5 .event edge, v0000000001108e60_19, v0000000001108e60_20, v0000000001108e60_21, v0000000001108e60_22;
v0000000001108e60_23 .array/port v0000000001108e60, 23;
v0000000001108e60_24 .array/port v0000000001108e60, 24;
v0000000001108e60_25 .array/port v0000000001108e60, 25;
v0000000001108e60_26 .array/port v0000000001108e60, 26;
E_00000000010e80c0/6 .event edge, v0000000001108e60_23, v0000000001108e60_24, v0000000001108e60_25, v0000000001108e60_26;
v0000000001108e60_27 .array/port v0000000001108e60, 27;
v0000000001108e60_28 .array/port v0000000001108e60, 28;
v0000000001108e60_29 .array/port v0000000001108e60, 29;
v0000000001108e60_30 .array/port v0000000001108e60, 30;
E_00000000010e80c0/7 .event edge, v0000000001108e60_27, v0000000001108e60_28, v0000000001108e60_29, v0000000001108e60_30;
v0000000001108e60_31 .array/port v0000000001108e60, 31;
E_00000000010e80c0/8 .event edge, v0000000001108e60_31, v00000000011092c0_0;
E_00000000010e80c0 .event/or E_00000000010e80c0/0, E_00000000010e80c0/1, E_00000000010e80c0/2, E_00000000010e80c0/3, E_00000000010e80c0/4, E_00000000010e80c0/5, E_00000000010e80c0/6, E_00000000010e80c0/7, E_00000000010e80c0/8;
S_0000000001099360 .scope begin, "$unm_blk_121" "$unm_blk_121" 8 16, 8 16 0, S_00000000010991d0;
.timescale 0 0;
v0000000001108dc0_0 .var/i "i", 31 0;
S_000000000108e6f0 .scope module, "ramInst" "mips_cpu_memory" 3 9, 9 1 0, S_000000000110ada0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 32 "data_address";
.port_info 2 /INPUT 1 "data_write";
.port_info 3 /INPUT 1 "data_read";
.port_info 4 /INPUT 32 "data_writedata";
.port_info 5 /OUTPUT 32 "data_readdata";
.port_info 6 /INPUT 32 "instr_address";
.port_info 7 /OUTPUT 32 "instr_readdata";
P_00000000010e8100 .param/str "RAM_INIT_FILE" 0 9 16, "inputs/o.txt";
L_00000000010ee230 .functor AND 1, L_00000000011660a0, L_0000000001165d80, C4<1>, C4<1>;
v0000000001163ff0_0 .net *"_ivl_0", 31 0, L_0000000001164f20; 1 drivers
L_00000000011679e8 .functor BUFT 1, C4<10111111110000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000000001163050_0 .net/2u *"_ivl_12", 31 0, L_00000000011679e8; 1 drivers
v0000000001164130_0 .net *"_ivl_14", 0 0, L_00000000011660a0; 1 drivers
L_0000000001167a30 .functor BUFT 1, C4<10111111110000000000000001000000>, C4<0>, C4<0>, C4<0>;
v0000000001164450_0 .net/2u *"_ivl_16", 31 0, L_0000000001167a30; 1 drivers
v0000000001163190_0 .net *"_ivl_18", 0 0, L_0000000001165d80; 1 drivers
v0000000001164630_0 .net *"_ivl_2", 31 0, L_00000000011654c0; 1 drivers
v0000000001163c30_0 .net *"_ivl_21", 0 0, L_00000000010ee230; 1 drivers
v0000000001163b90_0 .net *"_ivl_22", 31 0, L_00000000011661e0; 1 drivers
L_0000000001167a78 .functor BUFT 1, C4<10111111110000000000000000000000>, C4<0>, C4<0>, C4<0>;
v00000000011646d0_0 .net/2u *"_ivl_24", 31 0, L_0000000001167a78; 1 drivers
v0000000001164810_0 .net *"_ivl_26", 31 0, L_0000000001164b60; 1 drivers
v0000000001163230_0 .net *"_ivl_28", 31 0, L_0000000001166140; 1 drivers
v0000000001162970_0 .net *"_ivl_30", 29 0, L_0000000001165c40; 1 drivers
L_0000000001167ac0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v00000000011632d0_0 .net *"_ivl_32", 1 0, L_0000000001167ac0; 1 drivers
L_0000000001167b08 .functor BUFT 1, C4<xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>, C4<0>, C4<0>, C4<0>;
v0000000001163370_0 .net *"_ivl_34", 31 0, L_0000000001167b08; 1 drivers
v00000000011635f0_0 .net *"_ivl_4", 29 0, L_0000000001165e20; 1 drivers
L_0000000001167958 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000000001163cd0_0 .net *"_ivl_6", 1 0, L_0000000001167958; 1 drivers
L_00000000011679a0 .functor BUFT 1, C4<xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>, C4<0>, C4<0>, C4<0>;
v0000000001163690_0 .net *"_ivl_8", 31 0, L_00000000011679a0; 1 drivers
v0000000001163d70_0 .net "clk", 0 0, v0000000001166460_0; alias, 1 drivers
v0000000001163730_0 .net "data_address", 31 0, v0000000001109860_0; alias, 1 drivers
v00000000011637d0 .array "data_memory", 63 0, 31 0;
v0000000001163e10_0 .net "data_read", 0 0, v0000000001109900_0; alias, 1 drivers
v0000000001163f50_0 .net "data_readdata", 31 0, L_00000000011659c0; alias, 1 drivers
v0000000001163870_0 .net "data_write", 0 0, v0000000001109a40_0; alias, 1 drivers
v0000000001163910_0 .net "data_writedata", 31 0, v0000000001109c20_0; alias, 1 drivers
v0000000001164c00_0 .net "instr_address", 31 0, v0000000001162ab0_0; alias, 1 drivers
v00000000011665a0 .array "instr_memory", 63 0, 31 0;
v00000000011663c0_0 .net "instr_readdata", 31 0, L_0000000001165600; alias, 1 drivers
L_0000000001164f20 .array/port v00000000011637d0, L_00000000011654c0;
L_0000000001165e20 .part v0000000001109860_0, 2, 30;
L_00000000011654c0 .concat [ 30 2 0 0], L_0000000001165e20, L_0000000001167958;
L_00000000011659c0 .functor MUXZ 32, L_00000000011679a0, L_0000000001164f20, v0000000001109900_0, C4<>;
L_00000000011660a0 .cmp/ge 32, v0000000001162ab0_0, L_00000000011679e8;
L_0000000001165d80 .cmp/gt 32, L_0000000001167a30, v0000000001162ab0_0;
L_00000000011661e0 .array/port v00000000011665a0, L_0000000001166140;
L_0000000001164b60 .arith/sub 32, v0000000001162ab0_0, L_0000000001167a78;
L_0000000001165c40 .part L_0000000001164b60, 2, 30;
L_0000000001166140 .concat [ 30 2 0 0], L_0000000001165c40, L_0000000001167ac0;
L_0000000001165600 .functor MUXZ 32, L_0000000001167b08, L_00000000011661e0, L_00000000010ee230, C4<>;
S_0000000001052680 .scope begin, "$unm_blk_104" "$unm_blk_104" 9 21, 9 21 0, S_000000000108e6f0;
.timescale 0 0;
v0000000001163550_0 .var/i "i", 31 0;
S_0000000001052810 .scope begin, "$ivl_for_loop0" "$ivl_for_loop0" 9 36, 9 36 0, S_0000000001052680;
.timescale 0 0;
v0000000001163eb0_0 .var/i "j", 31 0;
.scope S_000000000108e6f0;
T_0 ;
%fork t_1, S_0000000001052680;
%jmp t_0;
.scope S_0000000001052680;
t_1 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001163550_0, 0, 32;
T_0.0 ;
%load/vec4 v0000000001163550_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_0.1, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 4, v0000000001163550_0;
%store/vec4a v00000000011637d0, 4, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001163550_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001163550_0, 0, 32;
%jmp T_0.0;
T_0.1 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001163550_0, 0, 32;
T_0.2 ;
%load/vec4 v0000000001163550_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_0.3, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 4, v0000000001163550_0;
%store/vec4a v00000000011665a0, 4, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001163550_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001163550_0, 0, 32;
%jmp T_0.2;
T_0.3 ;
%vpi_call/w 9 32 "$display", "RAM: Loading RAM contents from %s", P_00000000010e8100 {0 0 0};
%vpi_call/w 9 33 "$readmemh", P_00000000010e8100, v00000000011665a0 {0 0 0};
%fork t_3, S_0000000001052810;
%jmp t_2;
.scope S_0000000001052810;
t_3 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001163eb0_0, 0, 32;
T_0.4 ;
%load/vec4 v0000000001163eb0_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_0.5, 5;
%pushi/vec4 3217031168, 0, 32;
%load/vec4 v0000000001163eb0_0;
%muli 4, 0, 32;
%add;
%vpi_call/w 9 37 "$display", "byte +%h: %h", S<0,vec4,u32>, &A<v00000000011665a0, v0000000001163eb0_0 > {1 0 0};
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001163eb0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001163eb0_0, 0, 32;
%jmp T_0.4;
T_0.5 ;
%end;
.scope S_0000000001052680;
t_2 %join;
%end;
.scope S_000000000108e6f0;
t_0 %join;
%end;
.thread T_0;
.scope S_000000000108e6f0;
T_1 ;
%wait E_00000000010e8000;
%load/vec4 v0000000001163e10_0;
%nor/r;
%load/vec4 v0000000001163870_0;
%and;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0000000001164c00_0;
%load/vec4 v0000000001163730_0;
%cmp/ne;
%jmp/0xz T_1.2, 4;
%load/vec4 v0000000001163910_0;
%load/vec4 v0000000001163730_0;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v00000000011637d0, 0, 4;
T_1.2 ;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_00000000010a6150;
T_2 ;
%load/vec4 v0000000001109220_0;
%store/vec4 v0000000001109fe0_0, 0, 32;
%end;
.thread T_2;
.scope S_00000000010a6150;
T_3 ;
%wait E_00000000010e8000;
%load/vec4 v00000000011095e0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000000001108d20_0, 0;
%pushi/vec4 3217031168, 0, 32;
%assign/vec4 v0000000001109fe0_0, 0;
%jmp T_3.1;
T_3.0 ;
%load/vec4 v0000000001109fe0_0;
%cmpi/ne 0, 0, 32;
%jmp/0xz T_3.2, 4;
%load/vec4 v0000000001108d20_0;
%assign/vec4 v0000000001108d20_0, 0;
%load/vec4 v0000000001109d60_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_3.4, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_3.5, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_3.6, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_3.7, 6;
%jmp T_3.8;
T_3.4 ;
%load/vec4 v0000000001109fe0_0;
%assign/vec4 v0000000001109ea0_0, 0;
%load/vec4 v0000000001109ea0_0;
%addi 4, 0, 32;
%assign/vec4 v0000000001109fe0_0, 0;
%vpi_call/w 7 27 "$display", "New PC from %h to %h", v0000000001109ea0_0, v0000000001109fe0_0 {0 0 0};
%jmp T_3.8;
T_3.5 ;
%load/vec4 v0000000001109220_0;
%assign/vec4 v0000000001109fe0_0, 0;
%jmp T_3.8;
T_3.6 ;
%load/vec4 v0000000001109220_0;
%assign/vec4 v0000000001109fe0_0, 0;
%jmp T_3.8;
T_3.7 ;
%vpi_call/w 7 36 "$display", "JUMP REGISTER" {0 0 0};
%pushi/vec4 0, 0, 32;
%assign/vec4 v0000000001109fe0_0, 0;
%jmp T_3.8;
T_3.8 ;
%pop/vec4 1;
%jmp T_3.3;
T_3.2 ;
%load/vec4 v0000000001109fe0_0;
%cmpi/e 0, 0, 32;
%jmp/0xz T_3.9, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000000001108d20_0, 0;
T_3.9 ;
T_3.3 ;
T_3.1 ;
%jmp T_3;
.thread T_3;
.scope S_00000000010a5fc0;
T_4 ;
%wait E_00000000010e7040;
%vpi_call/w 6 86 "$display", "Opcode: %h", v0000000001109540_0 {0 0 0};
%load/vec4 v0000000001109540_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 32, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 15, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 11, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.0, 4;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000000001108960_0, 0, 2;
%vpi_call/w 6 89 "$display", "CTRLREGDST: Rt" {0 0 0};
%jmp T_4.1;
T_4.0 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 9, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.2, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000000001108960_0, 0, 2;
%vpi_call/w 6 92 "$display", "CTRLREGDST: Rd" {0 0 0};
%jmp T_4.3;
T_4.2 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 3, 0, 6;
%jmp/0xz T_4.4, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000000001108960_0, 0, 2;
%vpi_call/w 6 95 "$display", "CTRLREGDST: Link" {0 0 0};
%jmp T_4.5;
T_4.4 ;
%pushi/vec4 1, 1, 2;
%store/vec4 v0000000001108960_0, 0, 2;
%vpi_call/w 6 96 "$display", "xxxxxxxxxxxxxx" {0 0 0};
T_4.5 ;
T_4.3 ;
T_4.1 ;
%load/vec4 v0000000001109680_0;
%load/vec4 v0000000001109540_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109540_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109540_0;
%pushi/vec4 5, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109540_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 1, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 17, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 0, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 16, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.6, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000000001109cc0_0, 0, 2;
%jmp T_4.7;
T_4.6 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 2, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 3, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.8, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000000001109cc0_0, 0, 2;
%jmp T_4.9;
T_4.8 ;
%load/vec4 v0000000001108c80_0;
%cmpi/e 8, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001108c80_0;
%cmpi/e 9, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.10, 4;
%pushi/vec4 3, 0, 2;
%store/vec4 v0000000001109cc0_0, 0, 2;
%jmp T_4.11;
T_4.10 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000000001109cc0_0, 0, 2;
T_4.11 ;
T_4.9 ;
T_4.7 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 32, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.12, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a4e0_0, 0, 1;
%pushi/vec4 1, 0, 2;
%store/vec4 v000000000110a800_0, 0, 2;
%vpi_call/w 6 112 "$display", "Memory read enabled" {0 0 0};
%jmp T_4.13;
T_4.12 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 11, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 17, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 19, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.14, 9;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a4e0_0, 0, 1;
%pushi/vec4 0, 0, 2;
%store/vec4 v000000000110a800_0, 0, 2;
%vpi_call/w 6 116 "$display", "Memory read disabled" {0 0 0};
%jmp T_4.15;
T_4.14 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 3, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 9, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.16, 9;
%pushi/vec4 2, 0, 2;
%store/vec4 v000000000110a800_0, 0, 2;
%jmp T_4.17;
T_4.16 ;
%pushi/vec4 1, 1, 1;
%store/vec4 v000000000110a4e0_0, 0, 1;
T_4.17 ;
T_4.15 ;
T_4.13 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.18, 9;
%pushi/vec4 0, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%vpi_call/w 6 124 "$display", "ALU OP = 0 (ADDU/ADDIU)" {0 0 0};
%jmp T_4.19;
T_4.18 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 12, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.20, 9;
%pushi/vec4 4, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.21;
T_4.20 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 4, 0, 6;
%jmp/0xz T_4.22, 4;
%pushi/vec4 13, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.23;
T_4.22 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 1, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 17, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.24, 8;
%pushi/vec4 17, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.25;
T_4.24 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 7, 0, 6;
%jmp/0xz T_4.26, 4;
%pushi/vec4 16, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.27;
T_4.26 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 6, 0, 6;
%jmp/0xz T_4.28, 4;
%pushi/vec4 15, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.29;
T_4.28 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 0, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 16, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.30, 8;
%pushi/vec4 14, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.31;
T_4.30 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 5, 0, 6;
%jmp/0xz T_4.32, 4;
%pushi/vec4 18, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.33;
T_4.32 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.34, 8;
%pushi/vec4 3, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.35;
T_4.34 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.36, 8;
%pushi/vec4 23, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.37;
T_4.36 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 32, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 40, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 41, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 43, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.38, 4;
%pushi/vec4 0, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.39;
T_4.38 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 15, 0, 6;
%jmp/0xz T_4.40, 4;
%pushi/vec4 7, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.41;
T_4.40 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 17, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 19, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.42, 8;
%pushi/vec4 19, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.43;
T_4.42 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.44, 8;
%pushi/vec4 2, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.45;
T_4.44 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.46, 8;
%pushi/vec4 22, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.47;
T_4.46 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 13, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.48, 9;
%pushi/vec4 5, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.49;
T_4.48 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.50, 8;
%pushi/vec4 7, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.51;
T_4.50 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.52, 8;
%pushi/vec4 8, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.53;
T_4.52 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.54, 8;
%pushi/vec4 11, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.55;
T_4.54 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.56, 8;
%pushi/vec4 12, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.57;
T_4.56 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.58, 8;
%pushi/vec4 9, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.59;
T_4.58 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.60, 8;
%pushi/vec4 10, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.61;
T_4.60 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 10, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.62, 9;
%pushi/vec4 20, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.63;
T_4.62 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 11, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.64, 9;
%pushi/vec4 21, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.65;
T_4.64 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.66, 8;
%pushi/vec4 1, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%jmp T_4.67;
T_4.66 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 14, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.68, 9;
%pushi/vec4 6, 0, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
%vpi_call/w 6 175 "$display", "ALU Op = 6 (XOR)" {0 0 0};
%jmp T_4.69;
T_4.68 ;
%pushi/vec4 31, 31, 5;
%store/vec4 v0000000001108b40_0, 0, 5;
T_4.69 ;
T_4.67 ;
T_4.65 ;
T_4.63 ;
T_4.61 ;
T_4.59 ;
T_4.57 ;
T_4.55 ;
T_4.53 ;
T_4.51 ;
T_4.49 ;
T_4.47 ;
T_4.45 ;
T_4.43 ;
T_4.41 ;
T_4.39 ;
T_4.37 ;
T_4.35 ;
T_4.33 ;
T_4.31 ;
T_4.29 ;
T_4.27 ;
T_4.25 ;
T_4.23 ;
T_4.21 ;
T_4.19 ;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.70, 8;
%load/vec4 v0000000001109180_0;
%parti/s 5, 6, 4;
%store/vec4 v0000000001109e00_0, 0, 5;
%jmp T_4.71;
T_4.70 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 15, 0, 6;
%jmp/0xz T_4.72, 4;
%pushi/vec4 16, 0, 5;
%store/vec4 v0000000001109e00_0, 0, 5;
%jmp T_4.73;
T_4.72 ;
%pushi/vec4 31, 31, 5;
%store/vec4 v0000000001109e00_0, 0, 5;
T_4.73 ;
T_4.71 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 40, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 41, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 43, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.74, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000000001109040_0, 0, 1;
%jmp T_4.75;
T_4.74 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001109040_0, 0, 1;
T_4.75 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 15, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 11, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 32, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 40, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 41, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 43, 0, 6;
%flag_or 4, 8;
%jmp/0xz T_4.76, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000000011090e0_0, 0, 1;
%jmp T_4.77;
T_4.76 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 4, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 7, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 6, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 5, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%load/vec4 v0000000001109540_0;
%pushi/vec4 1, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 1, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 17, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 0, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001109f40_0;
%pushi/vec4 16, 0, 5;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 8;
%flag_or 8, 9;
%jmp/0xz T_4.78, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000000011090e0_0, 0, 1;
%jmp T_4.79;
T_4.78 ;
%pushi/vec4 1, 1, 1;
%store/vec4 v00000000011090e0_0, 0, 1;
T_4.79 ;
T_4.77 ;
%load/vec4 v0000000001109540_0;
%cmpi/e 9, 0, 6;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 12, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 32, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 36, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 33, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 37, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 15, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 35, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 34, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 38, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 13, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 10, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%cmpi/e 14, 0, 6;
%flag_or 4, 8;
%flag_mov 8, 4;
%load/vec4 v0000000001109540_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 33, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 36, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 26, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 27, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 24, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 25, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 37, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 0, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 4, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 42, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 43, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 3, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 7, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 2, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 6, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 35, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%load/vec4 v0000000001108c80_0;
%pushi/vec4 38, 0, 6;
%cmp/e;
%flag_get/vec4 4;
%or;
%and;
%flag_set/vec4 9;
%flag_or 9, 8;
%jmp/0xz T_4.80, 9;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a6c0_0, 0, 1;
%jmp T_4.81;
T_4.80 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a6c0_0, 0, 1;
T_4.81 ;
%jmp T_4;
.thread T_4, $push;
.scope S_00000000010991d0;
T_5 ;
%fork t_5, S_0000000001099360;
%jmp t_4;
.scope S_0000000001099360;
t_5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000000001108dc0_0, 0, 32;
T_5.0 ;
%load/vec4 v0000000001108dc0_0;
%cmpi/s 32, 0, 32;
%jmp/0xz T_5.1, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 4, v0000000001108dc0_0;
%store/vec4a v0000000001108e60, 4, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000000001108dc0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000000001108dc0_0, 0, 32;
%jmp T_5.0;
T_5.1 ;
%end;
.scope S_00000000010991d0;
t_4 %join;
%end;
.thread T_5;
.scope S_00000000010991d0;
T_6 ;
Ewait_0 .event/or E_00000000010e80c0, E_0x0;
%wait Ewait_0;
%load/vec4 v000000000110a440_0;
%pad/u 7;
%ix/vec4 4;
%load/vec4a v0000000001108e60, 4;
%store/vec4 v0000000001108f00_0, 0, 32;
%load/vec4 v00000000011092c0_0;
%pad/u 7;
%ix/vec4 4;
%load/vec4a v0000000001108e60, 4;
%store/vec4 v000000000110a120_0, 0, 32;
%jmp T_6;
.thread T_6, $push;
.scope S_00000000010991d0;
T_7 ;
%wait E_00000000010e7f80;
%load/vec4 v000000000110a3a0_0;
%cmpi/e 0, 0, 5;
%jmp/0xz T_7.0, 4;
%jmp T_7.1;
T_7.0 ;
%load/vec4 v0000000001109400_0;
%flag_set/vec4 8;
%jmp/0xz T_7.2, 8;
%load/vec4 v0000000001108a00_0;
%dup/vec4;
%pushi/vec4 32, 0, 6;
%cmp/u;
%jmp/1 T_7.4, 6;
%dup/vec4;
%pushi/vec4 36, 0, 6;
%cmp/u;
%jmp/1 T_7.5, 6;
%dup/vec4;
%pushi/vec4 33, 0, 6;
%cmp/u;
%jmp/1 T_7.6, 6;
%dup/vec4;
%pushi/vec4 37, 0, 6;
%cmp/u;
%jmp/1 T_7.7, 6;
%dup/vec4;
%pushi/vec4 34, 0, 6;
%cmp/u;
%jmp/1 T_7.8, 6;
%dup/vec4;
%pushi/vec4 38, 0, 6;
%cmp/u;
%jmp/1 T_7.9, 6;
%load/vec4 v000000000110a300_0;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.11;
T_7.4 ;
%load/vec4 v0000000001108f00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.12, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.13, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.14, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.15, 6;
%jmp T_7.16;
T_7.12 ;
%load/vec4 v000000000110a300_0;
%parti/s 1, 7, 4;
%replicate 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.16;
T_7.13 ;
%load/vec4 v000000000110a300_0;
%parti/s 1, 15, 5;
%replicate 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 8, 5;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.16;
T_7.14 ;
%load/vec4 v000000000110a300_0;
%parti/s 1, 23, 6;
%replicate 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.16;
T_7.15 ;
%load/vec4 v000000000110a300_0;
%parti/s 1, 31, 6;
%replicate 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 24, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.16;
T_7.16 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.5 ;
%load/vec4 v0000000001108f00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.17, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.18, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.19, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.20, 6;
%jmp T_7.21;
T_7.17 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.21;
T_7.18 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 8, 5;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.21;
T_7.19 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.21;
T_7.20 ;
%pushi/vec4 0, 0, 24;
%load/vec4 v000000000110a300_0;
%parti/s 8, 24, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.21;
T_7.21 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.6 ;
%load/vec4 v0000000001108f00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.22, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.23, 6;
%jmp T_7.24;
T_7.22 ;
%load/vec4 v000000000110a300_0;
%parti/s 1, 15, 5;
%replicate 16;
%load/vec4 v000000000110a300_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.24;
T_7.23 ;
%load/vec4 v000000000110a300_0;
%parti/s 1, 31, 6;
%replicate 16;
%load/vec4 v000000000110a300_0;
%parti/s 16, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.24;
T_7.24 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.7 ;
%load/vec4 v0000000001108f00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.25, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.26, 6;
%jmp T_7.27;
T_7.25 ;
%pushi/vec4 0, 0, 16;
%load/vec4 v000000000110a300_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.27;
T_7.26 ;
%pushi/vec4 0, 0, 16;
%load/vec4 v000000000110a300_0;
%parti/s 16, 16, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.27;
T_7.27 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.8 ;
%load/vec4 v0000000001108f00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.28, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.29, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.30, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.31, 6;
%jmp T_7.32;
T_7.28 ;
%load/vec4 v000000000110a300_0;
%parti/s 8, 0, 2;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 24, 0; part off
%ix/load 5, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 4, 5;
%jmp T_7.32;
T_7.29 ;
%load/vec4 v000000000110a300_0;
%parti/s 16, 0, 2;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 16, 0; part off
%ix/load 5, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 4, 5;
%jmp T_7.32;
T_7.30 ;
%load/vec4 v000000000110a300_0;
%parti/s 24, 0, 2;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 8, 0; part off
%ix/load 5, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 4, 5;
%jmp T_7.32;
T_7.31 ;
%load/vec4 v000000000110a300_0;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.32;
T_7.32 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.9 ;
%load/vec4 v0000000001108f00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_7.33, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_7.34, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_7.35, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_7.36, 6;
%jmp T_7.37;
T_7.33 ;
%load/vec4 v000000000110a300_0;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.37;
T_7.34 ;
%load/vec4 v000000000110a300_0;
%parti/s 24, 8, 5;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.37;
T_7.35 ;
%load/vec4 v000000000110a300_0;
%parti/s 16, 16, 6;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.37;
T_7.36 ;
%load/vec4 v000000000110a300_0;
%parti/s 8, 24, 6;
%load/vec4 v000000000110a3a0_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000000001108e60, 0, 4;
%jmp T_7.37;
T_7.37 ;
%pop/vec4 1;
%jmp T_7.11;
T_7.11 ;
%pop/vec4 1;
T_7.2 ;
T_7.1 ;
%jmp T_7;
.thread T_7;
.scope S_00000000010a5e30;
T_8 ;
Ewait_1 .event/or E_00000000010e7f00, E_0x0;
%wait Ewait_1;
%load/vec4 v0000000001108fa0_0;
%dup/vec4;
%pushi/vec4 0, 0, 5;
%cmp/u;
%jmp/1 T_8.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 5;
%cmp/u;
%jmp/1 T_8.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 5;
%cmp/u;
%jmp/1 T_8.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 5;
%cmp/u;
%jmp/1 T_8.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 5;
%cmp/u;
%jmp/1 T_8.4, 6;
%dup/vec4;
%pushi/vec4 5, 0, 5;
%cmp/u;
%jmp/1 T_8.5, 6;
%dup/vec4;
%pushi/vec4 6, 0, 5;
%cmp/u;
%jmp/1 T_8.6, 6;
%dup/vec4;
%pushi/vec4 7, 0, 5;
%cmp/u;
%jmp/1 T_8.7, 6;
%dup/vec4;
%pushi/vec4 8, 0, 5;
%cmp/u;
%jmp/1 T_8.8, 6;
%dup/vec4;
%pushi/vec4 9, 0, 5;
%cmp/u;
%jmp/1 T_8.9, 6;
%dup/vec4;
%pushi/vec4 10, 0, 5;
%cmp/u;
%jmp/1 T_8.10, 6;
%dup/vec4;
%pushi/vec4 11, 0, 5;
%cmp/u;
%jmp/1 T_8.11, 6;
%dup/vec4;
%pushi/vec4 12, 0, 5;
%cmp/u;
%jmp/1 T_8.12, 6;
%dup/vec4;
%pushi/vec4 13, 0, 5;
%cmp/u;
%jmp/1 T_8.13, 6;
%dup/vec4;
%pushi/vec4 14, 0, 5;
%cmp/u;
%jmp/1 T_8.14, 6;
%dup/vec4;
%pushi/vec4 15, 0, 5;
%cmp/u;
%jmp/1 T_8.15, 6;
%dup/vec4;
%pushi/vec4 16, 0, 5;
%cmp/u;
%jmp/1 T_8.16, 6;
%dup/vec4;
%pushi/vec4 17, 0, 5;
%cmp/u;
%jmp/1 T_8.17, 6;
%dup/vec4;
%pushi/vec4 18, 0, 5;
%cmp/u;
%jmp/1 T_8.18, 6;
%dup/vec4;
%pushi/vec4 19, 0, 5;
%cmp/u;
%jmp/1 T_8.19, 6;
%dup/vec4;
%pushi/vec4 20, 0, 5;
%cmp/u;
%jmp/1 T_8.20, 6;
%dup/vec4;
%pushi/vec4 21, 0, 5;
%cmp/u;
%jmp/1 T_8.21, 6;
%dup/vec4;
%pushi/vec4 22, 0, 5;
%cmp/u;
%jmp/1 T_8.22, 6;
%dup/vec4;
%pushi/vec4 23, 0, 5;
%cmp/u;
%jmp/1 T_8.23, 6;
%jmp T_8.24;
T_8.0 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%add;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.1 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%sub;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.2 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%mul;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.3 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%div/s;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.4 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%and;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.5 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%or;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.6 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%xor;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.7 ;
%load/vec4 v0000000001108be0_0;
%ix/getv 4, v000000000110a260_0;
%shiftl 4;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.8 ;
%load/vec4 v0000000001108be0_0;
%ix/getv 4, v000000000110a580_0;
%shiftl 4;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.9 ;
%load/vec4 v0000000001108be0_0;
%ix/getv 4, v000000000110a260_0;
%shiftr 4;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.10 ;
%load/vec4 v0000000001108be0_0;
%ix/getv 4, v000000000110a580_0;
%shiftr 4;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.11 ;
%load/vec4 v0000000001108be0_0;
%ix/getv 4, v000000000110a260_0;
%shiftr 4;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.12 ;
%load/vec4 v0000000001108be0_0;
%ix/getv 4, v000000000110a580_0;
%shiftr 4;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.13 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%cmp/e;
%jmp/0xz T_8.25, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
%jmp T_8.26;
T_8.25 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
T_8.26 ;
%jmp T_8.24;
T_8.14 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%cmp/s;
%jmp/0xz T_8.27, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
%jmp T_8.28;
T_8.27 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
T_8.28 ;
%jmp T_8.24;
T_8.15 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%cmp/s;
%flag_or 5, 4;
%jmp/0xz T_8.29, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
%jmp T_8.30;
T_8.29 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
T_8.30 ;
%jmp T_8.24;
T_8.16 ;
%load/vec4 v0000000001108be0_0;
%load/vec4 v000000000110a580_0;
%cmp/s;
%jmp/0xz T_8.31, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
%jmp T_8.32;
T_8.31 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
T_8.32 ;
%jmp T_8.24;
T_8.17 ;
%load/vec4 v0000000001108be0_0;
%load/vec4 v000000000110a580_0;
%cmp/s;
%flag_or 5, 4;
%jmp/0xz T_8.33, 5;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
%jmp T_8.34;
T_8.33 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
T_8.34 ;
%jmp T_8.24;
T_8.18 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%cmp/ne;
%jmp/0xz T_8.35, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
%jmp T_8.36;
T_8.35 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000000000110a1c0_0, 0, 1;
T_8.36 ;
%jmp T_8.24;
T_8.19 ;
%load/vec4 v000000000110a580_0;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.20 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%cmp/s;
%jmp/0xz T_8.37, 5;
%pushi/vec4 1, 0, 32;
%store/vec4 v0000000001109ae0_0, 0, 32;
T_8.37 ;
%jmp T_8.24;
T_8.21 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%cmp/u;
%jmp/0xz T_8.39, 5;
%pushi/vec4 1, 0, 32;
%store/vec4 v0000000001109ae0_0, 0, 32;
T_8.39 ;
%jmp T_8.24;
T_8.22 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%mul;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.23 ;
%load/vec4 v000000000110a580_0;
%load/vec4 v0000000001108be0_0;
%div;
%store/vec4 v0000000001109ae0_0, 0, 32;
%jmp T_8.24;
T_8.24 ;
%pop/vec4 1;
%jmp T_8;
.thread T_8, $push;
.scope S_000000000110af30;
T_9 ;
%pushi/vec4 3217031168, 0, 32;
%store/vec4 v0000000001164090_0, 0, 32;
%end;
.thread T_9, $init;
.scope S_000000000110af30;
T_10 ;
Ewait_2 .event/or E_00000000010e61c0, E_0x0;
%wait Ewait_2;
%load/vec4 v0000000001163af0_0;
%store/vec4 v0000000001162ab0_0, 0, 32;
%load/vec4 v0000000001162bf0_0;
%store/vec4 v0000000001109860_0, 0, 32;
%load/vec4 v0000000001162c90_0;
%store/vec4 v0000000001109a40_0, 0, 1;
%load/vec4 v00000000011643b0_0;
%store/vec4 v0000000001109900_0, 0, 1;
%load/vec4 v00000000011634b0_0;
%store/vec4 v0000000001109c20_0, 0, 32;
%jmp T_10;
.thread T_10, $push;
.scope S_000000000110af30;
T_11 ;
Ewait_3 .event/or E_00000000010e5c00, E_0x0;
%wait Ewait_3;
%load/vec4 v0000000001162a10_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_11.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_11.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_11.2, 6;
%jmp T_11.3;
T_11.0 ;
%load/vec4 v0000000001162d30_0;
%parti/s 5, 16, 6;
%store/vec4 v00000000011641d0_0, 0, 5;
%jmp T_11.3;
T_11.1 ;
%load/vec4 v0000000001162d30_0;
%parti/s 5, 11, 5;
%store/vec4 v00000000011641d0_0, 0, 5;
%jmp T_11.3;
T_11.2 ;
%pushi/vec4 31, 0, 5;
%store/vec4 v00000000011641d0_0, 0, 5;
%jmp T_11.3;
T_11.3 ;
%pop/vec4 1;
%load/vec4 v0000000001162e70_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_11.4, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_11.5, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_11.6, 6;
%jmp T_11.7;
T_11.4 ;
%load/vec4 v0000000001162bf0_0;
%store/vec4 v0000000001164310_0, 0, 32;
%jmp T_11.7;
T_11.5 ;
%load/vec4 v00000000011099a0_0;
%store/vec4 v0000000001164310_0, 0, 32;
%jmp T_11.7;
T_11.6 ;
%load/vec4 v0000000001164090_0;
%addi 8, 0, 32;
%store/vec4 v0000000001164310_0, 0, 32;
%jmp T_11.7;
T_11.7 ;
%pop/vec4 1;
%load/vec4 v0000000001164270_0;
%dup/vec4;
%pushi/vec4 1, 0, 1;
%cmp/u;
%jmp/1 T_11.8, 6;
%dup/vec4;
%pushi/vec4 0, 0, 1;
%cmp/u;
%jmp/1 T_11.9, 6;
%jmp T_11.10;
T_11.8 ;
%load/vec4 v0000000001162d30_0;
%parti/s 1, 15, 5;
%replicate 16;
%load/vec4 v0000000001162d30_0;
%parti/s 16, 0, 2;
%concat/vec4; draw_concat_vec4
%store/vec4 v00000000010ce2e0_0, 0, 32;
%jmp T_11.10;
T_11.9 ;
%load/vec4 v00000000011634b0_0;
%store/vec4 v00000000010ce2e0_0, 0, 32;
%jmp T_11.10;
T_11.10 ;
%pop/vec4 1;
%jmp T_11;
.thread T_11, $push;
.scope S_000000000110ada0;
T_12 ;
%vpi_call/w 3 36 "$dumpfile", "mips_cpu_harvard.vcd" {0 0 0};
%vpi_call/w 3 37 "$dumpvars", 32'sb00000000000000000000000000000000, S_000000000110ada0 {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0000000001166460_0, 0, 1;
%pushi/vec4 100, 0, 32;
T_12.0 %dup/vec4;
%pushi/vec4 0, 0, 32;
%cmp/s;
%jmp/1xz T_12.1, 5;
%jmp/1 T_12.1, 4;
%pushi/vec4 1, 0, 32;
%sub;
%delay 10, 0;
%load/vec4 v0000000001166460_0;
%nor/r;
%store/vec4 v0000000001166460_0, 0, 1;
%delay 10, 0;
%load/vec4 v0000000001166460_0;
%nor/r;
%store/vec4 v0000000001166460_0, 0, 1;
%jmp T_12.0;
T_12.1 ;
%pop/vec4 1;
%vpi_call/w 3 47 "$fatal", 32'sb00000000000000000000000000000010, "Simulation did not finish within %d cycles.", P_00000000010d97c8 {0 0 0};
%end;
.thread T_12;
.scope S_000000000110ada0;
T_13 ;
%vpi_call/w 3 51 "$display", "Initial Reset 0" {0 0 0};
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000000001166000_0, 0;
%vpi_call/w 3 55 "$display", "Initial Reset 1" {0 0 0};
%wait E_00000000010e8000;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000000001166000_0, 0;
%vpi_call/w 3 59 "$display", "Initial Reset 0: Start Program" {0 0 0};
%wait E_00000000010e8000;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000000001166000_0, 0;
%wait E_00000000010e8000;
%load/vec4 v0000000001165b00_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_13.0, 4;
%jmp T_13.1;
T_13.0 ;
%vpi_call/w 3 65 "$display", "TB: CPU did not set active=1 after reset." {0 0 0};
T_13.1 ;
T_13.2 ;
%load/vec4 v0000000001165b00_0;
%flag_set/vec4 8;
%jmp/0xz T_13.3, 8;
%wait E_00000000010e8000;
%vpi_call/w 3 71 "$display", "Reg File Write data: %d", v0000000001164310_0 {0 0 0};
%jmp T_13.2;
T_13.3 ;
%wait E_00000000010e8000;
%vpi_call/w 3 74 "$display", "TB: CPU Halt; active=0" {0 0 0};
%vpi_call/w 3 75 "$display", "Output:" {0 0 0};
%vpi_call/w 3 76 "$display", "%d", v0000000001165560_0 {0 0 0};
%vpi_call/w 3 77 "$finish" {0 0 0};
%end;
.thread T_13;
# The file index is used to find the file name in the following table.
:file_names 10;
"N/A";
"<interactive>";
"-";
"testbench/mips_cpu_harvard_tb.v";
"rtl/mips_cpu_harvard.v";
"rtl/mips_cpu_alu.v";
"rtl/mips_cpu_control.v";
"rtl/mips_cpu_pc.v";
"rtl/mips_cpu_regfile.v";
"rtl/mips_cpu_memory.v";
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