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46 lines
931 B
Verilog
46 lines
931 B
Verilog
module pc(
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input logic clk,
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input logic rst,
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input logic[1:0] pc_ctrl,
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input logic[31:0] pc_in,
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input logic[4:0] rs,
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output logic[31:0] pc_out,
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output logic active
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);
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reg [31:0] pc_curr;
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initial begin
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pc_out = pc_in;
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end // initial
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always_ff @(posedge clk) begin
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if (rst) begin
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active <= 1;
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pc_out <= 32'hBFC00000;
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end else if (pc_out != 32'd0) begin
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active <= active;
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case(pc_ctrl)
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2'd0: begin
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pc_curr <= pc_out;
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pc_out <= pc_curr + 32'd4;//No branch or jump or load, so no delay slot.
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$display("New PC from %h to %h", pc_curr, pc_out);
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end
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2'd1: begin
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pc_out <= pc_in;//Branches
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end
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2'd2: begin
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pc_out <= pc_in;//Jumps
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end
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2'd3: begin
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$display("JUMP REGISTER");
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pc_out <= 32'd0;//Jumps using register
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end
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endcase
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end else if (pc_out == 32'd0) begin
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active <= 0;
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//$display("CPU Halt");
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end
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end
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endmodule // pc
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