mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-11-10 01:35:49 +00:00
Update program counter
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
This commit is contained in:
jl7719
parent
3594365a25
commit
14ad7fa0ce
4
.gitignore
vendored
Normal file
4
.gitignore
vendored
Normal file
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@ -0,0 +1,4 @@
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exec/*
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inputs/*.log.txt
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inputs/*.out.txt
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mips_cpu_harvard.vcd
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60
MIPS.txt
60
MIPS.txt
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@ -1,60 +0,0 @@
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MIPS 32 bits
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== Bits, Bytes, Hex ==
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-- 8 bits = 1 byte = 2 hex
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-- 32 bits = 4 bytes = 8 hex
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-- e.g. 00000000 00000000 00000000 00000000 -> 0x00000000
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== CPU ==
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inputs:
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-- manual MIPS assembly code -> instructions in binaries
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-- C code -> compiled c program under mips -> disassemble binaries -> assembly code -> instruction in binaries
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-- these binary instructions goes into instruction memory
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outputs:
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-- output of the instructions
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errors:
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-- ?????? how do we detect errors ??????
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== Submodules ==
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-- ALU
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-- Register File
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-- Data Memory
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-- Instruction Register
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-- PC
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-- Control Unit
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== Testbench ==
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-- ????? not so sure yet ?????
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== Endianess ==
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-- big endian: bytes are numbered starting with byte 0 at MSB
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-- use -EB flag to ensure big endian
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== Instruction Access ==
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-- PC (program counter): 32 bit register
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-- PC is initialised to 0xBFC00000
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-- PC changed as instructions are executed
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-- IR = Mem[PC] -> instruction is fetched from data memory using data at the address given by program counter
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Address bus: CPU -> Memory
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Data bus: CPU <=> Memory
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== Register File ==
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-- 32 general-purpose registers
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== Program Counter ==
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-- PC is just a 32 bit register in which the value (address of instruction) get updated by other blocks
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-- Controlled by PCSrc (for branching or regular increment by 4 bytes)
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== Questions ==
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Pseudo-instructions -> how to deal with them -> convert to actual instructions?
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Do we implement big-endian mips?
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What verilator could be useful for
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How would a testbench in c++ be helpful?
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Don't understand that part where we need to implement cache
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== Todo ==
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Testbench in c++
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Cache
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CPU stall cycle
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,288 +0,0 @@
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RAM: Loading RAM contents from inputs/add.txt
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ERROR: rtl/mips_cpu_memory.v:33: $readmemh: Unable to open inputs/add.txt for reading.
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byte +bfc00000: 00000000
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byte +bfc00004: 00000000
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byte +bfc00008: 00000000
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byte +bfc0000c: 00000000
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byte +bfc00010: 00000000
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byte +bfc00014: 00000000
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byte +bfc00018: 00000000
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byte +bfc0001c: 00000000
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byte +bfc00020: 00000000
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byte +bfc00024: 00000000
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byte +bfc00028: 00000000
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byte +bfc0002c: 00000000
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byte +bfc00030: 00000000
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byte +bfc00034: 00000000
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byte +bfc00038: 00000000
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byte +bfc0003c: 00000000
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byte +bfc00040: 00000000
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byte +bfc00044: 00000000
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byte +bfc00048: 00000000
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byte +bfc0004c: 00000000
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byte +bfc00050: 00000000
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byte +bfc00054: 00000000
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byte +bfc00058: 00000000
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byte +bfc0005c: 00000000
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byte +bfc00060: 00000000
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byte +bfc00064: 00000000
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byte +bfc00068: 00000000
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byte +bfc0006c: 00000000
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byte +bfc00070: 00000000
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byte +bfc00074: 00000000
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byte +bfc00078: 00000000
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byte +bfc0007c: 00000000
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byte +bfc00080: 00000000
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byte +bfc00084: 00000000
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byte +bfc00088: 00000000
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byte +bfc0008c: 00000000
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byte +bfc00090: 00000000
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byte +bfc00094: 00000000
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byte +bfc00098: 00000000
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byte +bfc0009c: 00000000
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byte +bfc000a0: 00000000
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byte +bfc000a4: 00000000
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byte +bfc000a8: 00000000
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byte +bfc000ac: 00000000
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byte +bfc000b0: 00000000
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byte +bfc000b4: 00000000
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byte +bfc000b8: 00000000
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byte +bfc000bc: 00000000
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byte +bfc000c0: 00000000
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byte +bfc000c4: 00000000
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byte +bfc000c8: 00000000
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byte +bfc000cc: 00000000
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byte +bfc000d0: 00000000
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byte +bfc000d4: 00000000
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byte +bfc000d8: 00000000
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byte +bfc000dc: 00000000
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byte +bfc000e0: 00000000
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byte +bfc000e4: 00000000
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byte +bfc000e8: 00000000
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byte +bfc000ec: 00000000
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byte +bfc000f0: 00000000
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byte +bfc000f4: 00000000
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byte +bfc000f8: 00000000
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byte +bfc000fc: 00000000
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VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
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Initial Reset 0
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Initial Reset 1
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Opcode: xx
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xxxxxxxxxxxxxx
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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Initial Reset 0: Start Program
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New PC from xxxxxxxx to bfc00000
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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Opcode: xx
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xxxxxxxxxxxxxx
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Opcode: xx
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xxxxxxxxxxxxxx
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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New PC from bfc00000 to bfc00000
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New PC from bfc00000 to bfc00004
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00004 to bfc00004
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New PC from bfc00004 to bfc00008
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00008 to bfc00008
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New PC from bfc00008 to bfc0000c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0000c to bfc0000c
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New PC from bfc0000c to bfc00010
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00010 to bfc00010
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New PC from bfc00010 to bfc00014
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00014 to bfc00014
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New PC from bfc00014 to bfc00018
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00018 to bfc00018
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New PC from bfc00018 to bfc0001c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0001c to bfc0001c
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New PC from bfc0001c to bfc00020
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00020 to bfc00020
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New PC from bfc00020 to bfc00024
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00024 to bfc00024
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New PC from bfc00024 to bfc00028
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00028 to bfc00028
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New PC from bfc00028 to bfc0002c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0002c to bfc0002c
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New PC from bfc0002c to bfc00030
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00030 to bfc00030
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New PC from bfc00030 to bfc00034
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00034 to bfc00034
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New PC from bfc00034 to bfc00038
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00038 to bfc00038
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New PC from bfc00038 to bfc0003c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0003c to bfc0003c
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Opcode: 00
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CTRLREGDST: Rd
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Memory read disabled
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Opcode: xx
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xxxxxxxxxxxxxx
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New PC from bfc0003c to bfc00040
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00040 to bfc00040
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New PC from bfc00040 to bfc00044
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00044 to bfc00044
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New PC from bfc00044 to bfc00048
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00048 to bfc00048
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New PC from bfc00048 to bfc0004c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0004c to bfc0004c
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New PC from bfc0004c to bfc00050
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00050 to bfc00050
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New PC from bfc00050 to bfc00054
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00054 to bfc00054
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New PC from bfc00054 to bfc00058
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00058 to bfc00058
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New PC from bfc00058 to bfc0005c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0005c to bfc0005c
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New PC from bfc0005c to bfc00060
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00060 to bfc00060
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New PC from bfc00060 to bfc00064
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00064 to bfc00064
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New PC from bfc00064 to bfc00068
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00068 to bfc00068
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New PC from bfc00068 to bfc0006c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0006c to bfc0006c
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New PC from bfc0006c to bfc00070
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00070 to bfc00070
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New PC from bfc00070 to bfc00074
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00074 to bfc00074
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New PC from bfc00074 to bfc00078
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00078 to bfc00078
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New PC from bfc00078 to bfc0007c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0007c to bfc0007c
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New PC from bfc0007c to bfc00080
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00080 to bfc00080
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New PC from bfc00080 to bfc00084
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00084 to bfc00084
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New PC from bfc00084 to bfc00088
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00088 to bfc00088
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New PC from bfc00088 to bfc0008c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0008c to bfc0008c
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New PC from bfc0008c to bfc00090
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00090 to bfc00090
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New PC from bfc00090 to bfc00094
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00094 to bfc00094
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New PC from bfc00094 to bfc00098
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc00098 to bfc00098
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New PC from bfc00098 to bfc0009c
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc0009c to bfc0009c
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New PC from bfc0009c to bfc000a0
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000a0 to bfc000a0
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New PC from bfc000a0 to bfc000a4
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||||||
Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000a4 to bfc000a4
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New PC from bfc000a4 to bfc000a8
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||||||
Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000a8 to bfc000a8
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New PC from bfc000a8 to bfc000ac
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000ac to bfc000ac
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New PC from bfc000ac to bfc000b0
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000b0 to bfc000b0
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New PC from bfc000b0 to bfc000b4
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||||||
Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000b4 to bfc000b4
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New PC from bfc000b4 to bfc000b8
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||||||
Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000b8 to bfc000b8
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New PC from bfc000b8 to bfc000bc
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000bc to bfc000bc
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New PC from bfc000bc to bfc000c0
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Reg File Write data: x
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Reg File Write data: x
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New PC from bfc000c0 to bfc000c0
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New PC from bfc000c0 to bfc000c4
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Reg File Write data: x
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FATAL: testbench/mips_cpu_harvard_tb.v:47: Simulation did not finish within 100 cycles.
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Time: 2000 Scope: mips_cpu_harvard_tb
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||||||
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@ -1 +0,0 @@
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||||||
Time: 2000 Scope: mips_cpu_harvard_tb
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|
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@ -1,181 +0,0 @@
|
||||||
RAM: Loading RAM contents from inputs/addiu.txt
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|
||||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/addiu.txt): Not enough words in the file for the requested range [0:63].
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|
||||||
byte +bfc00000: 3404000a
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byte +bfc00004: 24820014
|
|
||||||
byte +bfc00008: 00000008
|
|
||||||
byte +bfc0000c: 00000000
|
|
||||||
byte +bfc00010: 00000000
|
|
||||||
byte +bfc00014: 00000000
|
|
||||||
byte +bfc00018: 00000000
|
|
||||||
byte +bfc0001c: 00000000
|
|
||||||
byte +bfc00020: 00000000
|
|
||||||
byte +bfc00024: 00000000
|
|
||||||
byte +bfc00028: 00000000
|
|
||||||
byte +bfc0002c: 00000000
|
|
||||||
byte +bfc00030: 00000000
|
|
||||||
byte +bfc00034: 00000000
|
|
||||||
byte +bfc00038: 00000000
|
|
||||||
byte +bfc0003c: 00000000
|
|
||||||
byte +bfc00040: 00000000
|
|
||||||
byte +bfc00044: 00000000
|
|
||||||
byte +bfc00048: 00000000
|
|
||||||
byte +bfc0004c: 00000000
|
|
||||||
byte +bfc00050: 00000000
|
|
||||||
byte +bfc00054: 00000000
|
|
||||||
byte +bfc00058: 00000000
|
|
||||||
byte +bfc0005c: 00000000
|
|
||||||
byte +bfc00060: 00000000
|
|
||||||
byte +bfc00064: 00000000
|
|
||||||
byte +bfc00068: 00000000
|
|
||||||
byte +bfc0006c: 00000000
|
|
||||||
byte +bfc00070: 00000000
|
|
||||||
byte +bfc00074: 00000000
|
|
||||||
byte +bfc00078: 00000000
|
|
||||||
byte +bfc0007c: 00000000
|
|
||||||
byte +bfc00080: 00000000
|
|
||||||
byte +bfc00084: 00000000
|
|
||||||
byte +bfc00088: 00000000
|
|
||||||
byte +bfc0008c: 00000000
|
|
||||||
byte +bfc00090: 00000000
|
|
||||||
byte +bfc00094: 00000000
|
|
||||||
byte +bfc00098: 00000000
|
|
||||||
byte +bfc0009c: 00000000
|
|
||||||
byte +bfc000a0: 00000000
|
|
||||||
byte +bfc000a4: 00000000
|
|
||||||
byte +bfc000a8: 00000000
|
|
||||||
byte +bfc000ac: 00000000
|
|
||||||
byte +bfc000b0: 00000000
|
|
||||||
byte +bfc000b4: 00000000
|
|
||||||
byte +bfc000b8: 00000000
|
|
||||||
byte +bfc000bc: 00000000
|
|
||||||
byte +bfc000c0: 00000000
|
|
||||||
byte +bfc000c4: 00000000
|
|
||||||
byte +bfc000c8: 00000000
|
|
||||||
byte +bfc000cc: 00000000
|
|
||||||
byte +bfc000d0: 00000000
|
|
||||||
byte +bfc000d4: 00000000
|
|
||||||
byte +bfc000d8: 00000000
|
|
||||||
byte +bfc000dc: 00000000
|
|
||||||
byte +bfc000e0: 00000000
|
|
||||||
byte +bfc000e4: 00000000
|
|
||||||
byte +bfc000e8: 00000000
|
|
||||||
byte +bfc000ec: 00000000
|
|
||||||
byte +bfc000f0: 00000000
|
|
||||||
byte +bfc000f4: 00000000
|
|
||||||
byte +bfc000f8: 00000000
|
|
||||||
byte +bfc000fc: 00000000
|
|
||||||
MEM: Loading MEM contents from inputs/addiu.data.txt
|
|
||||||
WARNING: rtl/mips_cpu_memory.v:42: $readmemh(inputs/addiu.data.txt): Not enough words in the file for the requested range [0:63].
|
|
||||||
byte +00001000: 12341234
|
|
||||||
byte +00001004: 01010101
|
|
||||||
byte +00001008: 12312312
|
|
||||||
byte +0000100c: 88888888
|
|
||||||
byte +00001010: 00000000
|
|
||||||
byte +00001014: 00000000
|
|
||||||
byte +00001018: 00000000
|
|
||||||
byte +0000101c: 00000000
|
|
||||||
byte +00001020: 00000000
|
|
||||||
byte +00001024: 00000000
|
|
||||||
byte +00001028: 00000000
|
|
||||||
byte +0000102c: 00000000
|
|
||||||
byte +00001030: 00000000
|
|
||||||
byte +00001034: 00000000
|
|
||||||
byte +00001038: 00000000
|
|
||||||
byte +0000103c: 00000000
|
|
||||||
byte +00001040: 00000000
|
|
||||||
byte +00001044: 00000000
|
|
||||||
byte +00001048: 00000000
|
|
||||||
byte +0000104c: 00000000
|
|
||||||
byte +00001050: 00000000
|
|
||||||
byte +00001054: 00000000
|
|
||||||
byte +00001058: 00000000
|
|
||||||
byte +0000105c: 00000000
|
|
||||||
byte +00001060: 00000000
|
|
||||||
byte +00001064: 00000000
|
|
||||||
byte +00001068: 00000000
|
|
||||||
byte +0000106c: 00000000
|
|
||||||
byte +00001070: 00000000
|
|
||||||
byte +00001074: 00000000
|
|
||||||
byte +00001078: 00000000
|
|
||||||
byte +0000107c: 00000000
|
|
||||||
byte +00001080: 00000000
|
|
||||||
byte +00001084: 00000000
|
|
||||||
byte +00001088: 00000000
|
|
||||||
byte +0000108c: 00000000
|
|
||||||
byte +00001090: 00000000
|
|
||||||
byte +00001094: 00000000
|
|
||||||
byte +00001098: 00000000
|
|
||||||
byte +0000109c: 00000000
|
|
||||||
byte +000010a0: 00000000
|
|
||||||
byte +000010a4: 00000000
|
|
||||||
byte +000010a8: 00000000
|
|
||||||
byte +000010ac: 00000000
|
|
||||||
byte +000010b0: 00000000
|
|
||||||
byte +000010b4: 00000000
|
|
||||||
byte +000010b8: 00000000
|
|
||||||
byte +000010bc: 00000000
|
|
||||||
byte +000010c0: 00000000
|
|
||||||
byte +000010c4: 00000000
|
|
||||||
byte +000010c8: 00000000
|
|
||||||
byte +000010cc: 00000000
|
|
||||||
byte +000010d0: 00000000
|
|
||||||
byte +000010d4: 00000000
|
|
||||||
byte +000010d8: 00000000
|
|
||||||
byte +000010dc: 00000000
|
|
||||||
byte +000010e0: 00000000
|
|
||||||
byte +000010e4: 00000000
|
|
||||||
byte +000010e8: 00000000
|
|
||||||
byte +000010ec: 00000000
|
|
||||||
byte +000010f0: 00000000
|
|
||||||
byte +000010f4: 00000000
|
|
||||||
byte +000010f8: 00000000
|
|
||||||
byte +000010fc: 00000000
|
|
||||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
|
||||||
Initial Reset 0
|
|
||||||
Initial Reset 1
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Initial Reset 0: Start Program
|
|
||||||
New PC from xxxxxxxx to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 09
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
ALU OP = 0 (ADDU/ADDIU)
|
|
||||||
New PC from bfc00000 to bfc00004
|
|
||||||
Reg File Write data: 30
|
|
||||||
Reg File Write data: 30
|
|
||||||
New PC from bfc00004 to bfc00004
|
|
||||||
Opcode: 09
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
ALU OP = 0 (ADDU/ADDIU)
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
JUMP REGISTER
|
|
||||||
Reg File Write data: 18
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Reg File Write data: 18
|
|
||||||
Reg File Write data: 18
|
|
||||||
TB: CPU Halt; active=0
|
|
||||||
Output:
|
|
||||||
30
|
|
||||||
|
|
@ -1 +0,0 @@
|
||||||
30
|
|
||||||
|
|
@ -1,125 +0,0 @@
|
||||||
RAM: Loading RAM contents from inputs/addu.txt
|
|
||||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/addu.txt): Not enough words in the file for the requested range [0:63].
|
|
||||||
byte +bfc00000: 3404ffff
|
|
||||||
byte +bfc00004: 3405f000
|
|
||||||
byte +bfc00008: 00851021
|
|
||||||
byte +bfc0000c: 00000008
|
|
||||||
byte +bfc00010: 00000000
|
|
||||||
byte +bfc00014: 00000000
|
|
||||||
byte +bfc00018: 00000000
|
|
||||||
byte +bfc0001c: 00000000
|
|
||||||
byte +bfc00020: 00000000
|
|
||||||
byte +bfc00024: 00000000
|
|
||||||
byte +bfc00028: 00000000
|
|
||||||
byte +bfc0002c: 00000000
|
|
||||||
byte +bfc00030: 00000000
|
|
||||||
byte +bfc00034: 00000000
|
|
||||||
byte +bfc00038: 00000000
|
|
||||||
byte +bfc0003c: 00000000
|
|
||||||
byte +bfc00040: 00000000
|
|
||||||
byte +bfc00044: 00000000
|
|
||||||
byte +bfc00048: 00000000
|
|
||||||
byte +bfc0004c: 00000000
|
|
||||||
byte +bfc00050: 00000000
|
|
||||||
byte +bfc00054: 00000000
|
|
||||||
byte +bfc00058: 00000000
|
|
||||||
byte +bfc0005c: 00000000
|
|
||||||
byte +bfc00060: 00000000
|
|
||||||
byte +bfc00064: 00000000
|
|
||||||
byte +bfc00068: 00000000
|
|
||||||
byte +bfc0006c: 00000000
|
|
||||||
byte +bfc00070: 00000000
|
|
||||||
byte +bfc00074: 00000000
|
|
||||||
byte +bfc00078: 00000000
|
|
||||||
byte +bfc0007c: 00000000
|
|
||||||
byte +bfc00080: 00000000
|
|
||||||
byte +bfc00084: 00000000
|
|
||||||
byte +bfc00088: 00000000
|
|
||||||
byte +bfc0008c: 00000000
|
|
||||||
byte +bfc00090: 00000000
|
|
||||||
byte +bfc00094: 00000000
|
|
||||||
byte +bfc00098: 00000000
|
|
||||||
byte +bfc0009c: 00000000
|
|
||||||
byte +bfc000a0: 00000000
|
|
||||||
byte +bfc000a4: 00000000
|
|
||||||
byte +bfc000a8: 00000000
|
|
||||||
byte +bfc000ac: 00000000
|
|
||||||
byte +bfc000b0: 00000000
|
|
||||||
byte +bfc000b4: 00000000
|
|
||||||
byte +bfc000b8: 00000000
|
|
||||||
byte +bfc000bc: 00000000
|
|
||||||
byte +bfc000c0: 00000000
|
|
||||||
byte +bfc000c4: 00000000
|
|
||||||
byte +bfc000c8: 00000000
|
|
||||||
byte +bfc000cc: 00000000
|
|
||||||
byte +bfc000d0: 00000000
|
|
||||||
byte +bfc000d4: 00000000
|
|
||||||
byte +bfc000d8: 00000000
|
|
||||||
byte +bfc000dc: 00000000
|
|
||||||
byte +bfc000e0: 00000000
|
|
||||||
byte +bfc000e4: 00000000
|
|
||||||
byte +bfc000e8: 00000000
|
|
||||||
byte +bfc000ec: 00000000
|
|
||||||
byte +bfc000f0: 00000000
|
|
||||||
byte +bfc000f4: 00000000
|
|
||||||
byte +bfc000f8: 00000000
|
|
||||||
byte +bfc000fc: 00000000
|
|
||||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
|
||||||
Initial Reset 0
|
|
||||||
Initial Reset 1
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Initial Reset 0: Start Program
|
|
||||||
New PC from xxxxxxxx to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00004
|
|
||||||
Reg File Write data: 4294963200
|
|
||||||
Reg File Write data: 4294963200
|
|
||||||
New PC from bfc00004 to bfc00004
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
ALU OP = 0 (ADDU/ADDIU)
|
|
||||||
New PC from bfc00004 to bfc00008
|
|
||||||
Reg File Write data: 4294963199
|
|
||||||
Reg File Write data: 4294963199
|
|
||||||
New PC from bfc00008 to bfc00008
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
ALU OP = 0 (ADDU/ADDIU)
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
JUMP REGISTER
|
|
||||||
Reg File Write data: 4294963199
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Reg File Write data: 4294963199
|
|
||||||
Reg File Write data: 4294963199
|
|
||||||
TB: CPU Halt; active=0
|
|
||||||
Output:
|
|
||||||
4294963199
|
|
||||||
|
|
@ -1 +0,0 @@
|
||||||
4294963199
|
|
||||||
|
|
@ -1,123 +0,0 @@
|
||||||
RAM: Loading RAM contents from inputs/and.txt
|
|
||||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/and.txt): Not enough words in the file for the requested range [0:63].
|
|
||||||
byte +bfc00000: 3404000a
|
|
||||||
byte +bfc00004: 3405000f
|
|
||||||
byte +bfc00008: 00851024
|
|
||||||
byte +bfc0000c: 00000008
|
|
||||||
byte +bfc00010: 00000000
|
|
||||||
byte +bfc00014: 00000000
|
|
||||||
byte +bfc00018: 00000000
|
|
||||||
byte +bfc0001c: 00000000
|
|
||||||
byte +bfc00020: 00000000
|
|
||||||
byte +bfc00024: 00000000
|
|
||||||
byte +bfc00028: 00000000
|
|
||||||
byte +bfc0002c: 00000000
|
|
||||||
byte +bfc00030: 00000000
|
|
||||||
byte +bfc00034: 00000000
|
|
||||||
byte +bfc00038: 00000000
|
|
||||||
byte +bfc0003c: 00000000
|
|
||||||
byte +bfc00040: 00000000
|
|
||||||
byte +bfc00044: 00000000
|
|
||||||
byte +bfc00048: 00000000
|
|
||||||
byte +bfc0004c: 00000000
|
|
||||||
byte +bfc00050: 00000000
|
|
||||||
byte +bfc00054: 00000000
|
|
||||||
byte +bfc00058: 00000000
|
|
||||||
byte +bfc0005c: 00000000
|
|
||||||
byte +bfc00060: 00000000
|
|
||||||
byte +bfc00064: 00000000
|
|
||||||
byte +bfc00068: 00000000
|
|
||||||
byte +bfc0006c: 00000000
|
|
||||||
byte +bfc00070: 00000000
|
|
||||||
byte +bfc00074: 00000000
|
|
||||||
byte +bfc00078: 00000000
|
|
||||||
byte +bfc0007c: 00000000
|
|
||||||
byte +bfc00080: 00000000
|
|
||||||
byte +bfc00084: 00000000
|
|
||||||
byte +bfc00088: 00000000
|
|
||||||
byte +bfc0008c: 00000000
|
|
||||||
byte +bfc00090: 00000000
|
|
||||||
byte +bfc00094: 00000000
|
|
||||||
byte +bfc00098: 00000000
|
|
||||||
byte +bfc0009c: 00000000
|
|
||||||
byte +bfc000a0: 00000000
|
|
||||||
byte +bfc000a4: 00000000
|
|
||||||
byte +bfc000a8: 00000000
|
|
||||||
byte +bfc000ac: 00000000
|
|
||||||
byte +bfc000b0: 00000000
|
|
||||||
byte +bfc000b4: 00000000
|
|
||||||
byte +bfc000b8: 00000000
|
|
||||||
byte +bfc000bc: 00000000
|
|
||||||
byte +bfc000c0: 00000000
|
|
||||||
byte +bfc000c4: 00000000
|
|
||||||
byte +bfc000c8: 00000000
|
|
||||||
byte +bfc000cc: 00000000
|
|
||||||
byte +bfc000d0: 00000000
|
|
||||||
byte +bfc000d4: 00000000
|
|
||||||
byte +bfc000d8: 00000000
|
|
||||||
byte +bfc000dc: 00000000
|
|
||||||
byte +bfc000e0: 00000000
|
|
||||||
byte +bfc000e4: 00000000
|
|
||||||
byte +bfc000e8: 00000000
|
|
||||||
byte +bfc000ec: 00000000
|
|
||||||
byte +bfc000f0: 00000000
|
|
||||||
byte +bfc000f4: 00000000
|
|
||||||
byte +bfc000f8: 00000000
|
|
||||||
byte +bfc000fc: 00000000
|
|
||||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
|
||||||
Initial Reset 0
|
|
||||||
Initial Reset 1
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Initial Reset 0: Start Program
|
|
||||||
New PC from xxxxxxxx to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00004
|
|
||||||
Reg File Write data: 15
|
|
||||||
Reg File Write data: 15
|
|
||||||
New PC from bfc00004 to bfc00004
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00004 to bfc00008
|
|
||||||
Reg File Write data: 10
|
|
||||||
Reg File Write data: 10
|
|
||||||
New PC from bfc00008 to bfc00008
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
JUMP REGISTER
|
|
||||||
Reg File Write data: 10
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Reg File Write data: 10
|
|
||||||
Reg File Write data: 10
|
|
||||||
TB: CPU Halt; active=0
|
|
||||||
Output:
|
|
||||||
10
|
|
||||||
|
|
@ -1 +0,0 @@
|
||||||
10
|
|
||||||
|
|
@ -1,113 +0,0 @@
|
||||||
RAM: Loading RAM contents from inputs/andi.txt
|
|
||||||
WARNING: rtl/mips_cpu_memory.v:33: $readmemh(inputs/andi.txt): Not enough words in the file for the requested range [0:63].
|
|
||||||
byte +bfc00000: 34040005
|
|
||||||
byte +bfc00004: 3082000f
|
|
||||||
byte +bfc00008: 00000008
|
|
||||||
byte +bfc0000c: 00000000
|
|
||||||
byte +bfc00010: 00000000
|
|
||||||
byte +bfc00014: 00000000
|
|
||||||
byte +bfc00018: 00000000
|
|
||||||
byte +bfc0001c: 00000000
|
|
||||||
byte +bfc00020: 00000000
|
|
||||||
byte +bfc00024: 00000000
|
|
||||||
byte +bfc00028: 00000000
|
|
||||||
byte +bfc0002c: 00000000
|
|
||||||
byte +bfc00030: 00000000
|
|
||||||
byte +bfc00034: 00000000
|
|
||||||
byte +bfc00038: 00000000
|
|
||||||
byte +bfc0003c: 00000000
|
|
||||||
byte +bfc00040: 00000000
|
|
||||||
byte +bfc00044: 00000000
|
|
||||||
byte +bfc00048: 00000000
|
|
||||||
byte +bfc0004c: 00000000
|
|
||||||
byte +bfc00050: 00000000
|
|
||||||
byte +bfc00054: 00000000
|
|
||||||
byte +bfc00058: 00000000
|
|
||||||
byte +bfc0005c: 00000000
|
|
||||||
byte +bfc00060: 00000000
|
|
||||||
byte +bfc00064: 00000000
|
|
||||||
byte +bfc00068: 00000000
|
|
||||||
byte +bfc0006c: 00000000
|
|
||||||
byte +bfc00070: 00000000
|
|
||||||
byte +bfc00074: 00000000
|
|
||||||
byte +bfc00078: 00000000
|
|
||||||
byte +bfc0007c: 00000000
|
|
||||||
byte +bfc00080: 00000000
|
|
||||||
byte +bfc00084: 00000000
|
|
||||||
byte +bfc00088: 00000000
|
|
||||||
byte +bfc0008c: 00000000
|
|
||||||
byte +bfc00090: 00000000
|
|
||||||
byte +bfc00094: 00000000
|
|
||||||
byte +bfc00098: 00000000
|
|
||||||
byte +bfc0009c: 00000000
|
|
||||||
byte +bfc000a0: 00000000
|
|
||||||
byte +bfc000a4: 00000000
|
|
||||||
byte +bfc000a8: 00000000
|
|
||||||
byte +bfc000ac: 00000000
|
|
||||||
byte +bfc000b0: 00000000
|
|
||||||
byte +bfc000b4: 00000000
|
|
||||||
byte +bfc000b8: 00000000
|
|
||||||
byte +bfc000bc: 00000000
|
|
||||||
byte +bfc000c0: 00000000
|
|
||||||
byte +bfc000c4: 00000000
|
|
||||||
byte +bfc000c8: 00000000
|
|
||||||
byte +bfc000cc: 00000000
|
|
||||||
byte +bfc000d0: 00000000
|
|
||||||
byte +bfc000d4: 00000000
|
|
||||||
byte +bfc000d8: 00000000
|
|
||||||
byte +bfc000dc: 00000000
|
|
||||||
byte +bfc000e0: 00000000
|
|
||||||
byte +bfc000e4: 00000000
|
|
||||||
byte +bfc000e8: 00000000
|
|
||||||
byte +bfc000ec: 00000000
|
|
||||||
byte +bfc000f0: 00000000
|
|
||||||
byte +bfc000f4: 00000000
|
|
||||||
byte +bfc000f8: 00000000
|
|
||||||
byte +bfc000fc: 00000000
|
|
||||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
|
||||||
Initial Reset 0
|
|
||||||
Initial Reset 1
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Initial Reset 0: Start Program
|
|
||||||
New PC from xxxxxxxx to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00000
|
|
||||||
Opcode: 0d
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 0c
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00004
|
|
||||||
Reg File Write data: 5
|
|
||||||
Reg File Write data: 5
|
|
||||||
New PC from bfc00004 to bfc00004
|
|
||||||
Opcode: 0c
|
|
||||||
CTRLREGDST: Rt
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
JUMP REGISTER
|
|
||||||
Reg File Write data: 0
|
|
||||||
Opcode: 00
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Reg File Write data: 0
|
|
||||||
Reg File Write data: 0
|
|
||||||
TB: CPU Halt; active=0
|
|
||||||
Output:
|
|
||||||
5
|
|
||||||
|
|
@ -1 +0,0 @@
|
||||||
5
|
|
||||||
|
|
@ -1,288 +0,0 @@
|
||||||
RAM: Loading RAM contents from inputs/andiu.txt
|
|
||||||
ERROR: rtl/mips_cpu_memory.v:33: $readmemh: Unable to open inputs/andiu.txt for reading.
|
|
||||||
byte +bfc00000: 00000000
|
|
||||||
byte +bfc00004: 00000000
|
|
||||||
byte +bfc00008: 00000000
|
|
||||||
byte +bfc0000c: 00000000
|
|
||||||
byte +bfc00010: 00000000
|
|
||||||
byte +bfc00014: 00000000
|
|
||||||
byte +bfc00018: 00000000
|
|
||||||
byte +bfc0001c: 00000000
|
|
||||||
byte +bfc00020: 00000000
|
|
||||||
byte +bfc00024: 00000000
|
|
||||||
byte +bfc00028: 00000000
|
|
||||||
byte +bfc0002c: 00000000
|
|
||||||
byte +bfc00030: 00000000
|
|
||||||
byte +bfc00034: 00000000
|
|
||||||
byte +bfc00038: 00000000
|
|
||||||
byte +bfc0003c: 00000000
|
|
||||||
byte +bfc00040: 00000000
|
|
||||||
byte +bfc00044: 00000000
|
|
||||||
byte +bfc00048: 00000000
|
|
||||||
byte +bfc0004c: 00000000
|
|
||||||
byte +bfc00050: 00000000
|
|
||||||
byte +bfc00054: 00000000
|
|
||||||
byte +bfc00058: 00000000
|
|
||||||
byte +bfc0005c: 00000000
|
|
||||||
byte +bfc00060: 00000000
|
|
||||||
byte +bfc00064: 00000000
|
|
||||||
byte +bfc00068: 00000000
|
|
||||||
byte +bfc0006c: 00000000
|
|
||||||
byte +bfc00070: 00000000
|
|
||||||
byte +bfc00074: 00000000
|
|
||||||
byte +bfc00078: 00000000
|
|
||||||
byte +bfc0007c: 00000000
|
|
||||||
byte +bfc00080: 00000000
|
|
||||||
byte +bfc00084: 00000000
|
|
||||||
byte +bfc00088: 00000000
|
|
||||||
byte +bfc0008c: 00000000
|
|
||||||
byte +bfc00090: 00000000
|
|
||||||
byte +bfc00094: 00000000
|
|
||||||
byte +bfc00098: 00000000
|
|
||||||
byte +bfc0009c: 00000000
|
|
||||||
byte +bfc000a0: 00000000
|
|
||||||
byte +bfc000a4: 00000000
|
|
||||||
byte +bfc000a8: 00000000
|
|
||||||
byte +bfc000ac: 00000000
|
|
||||||
byte +bfc000b0: 00000000
|
|
||||||
byte +bfc000b4: 00000000
|
|
||||||
byte +bfc000b8: 00000000
|
|
||||||
byte +bfc000bc: 00000000
|
|
||||||
byte +bfc000c0: 00000000
|
|
||||||
byte +bfc000c4: 00000000
|
|
||||||
byte +bfc000c8: 00000000
|
|
||||||
byte +bfc000cc: 00000000
|
|
||||||
byte +bfc000d0: 00000000
|
|
||||||
byte +bfc000d4: 00000000
|
|
||||||
byte +bfc000d8: 00000000
|
|
||||||
byte +bfc000dc: 00000000
|
|
||||||
byte +bfc000e0: 00000000
|
|
||||||
byte +bfc000e4: 00000000
|
|
||||||
byte +bfc000e8: 00000000
|
|
||||||
byte +bfc000ec: 00000000
|
|
||||||
byte +bfc000f0: 00000000
|
|
||||||
byte +bfc000f4: 00000000
|
|
||||||
byte +bfc000f8: 00000000
|
|
||||||
byte +bfc000fc: 00000000
|
|
||||||
VCD info: dumpfile mips_cpu_harvard.vcd opened for output.
|
|
||||||
Initial Reset 0
|
|
||||||
Initial Reset 1
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
Initial Reset 0: Start Program
|
|
||||||
New PC from xxxxxxxx to bfc00000
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
New PC from bfc00000 to bfc00000
|
|
||||||
New PC from bfc00000 to bfc00004
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00004 to bfc00004
|
|
||||||
New PC from bfc00004 to bfc00008
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00008 to bfc00008
|
|
||||||
New PC from bfc00008 to bfc0000c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0000c to bfc0000c
|
|
||||||
New PC from bfc0000c to bfc00010
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00010 to bfc00010
|
|
||||||
New PC from bfc00010 to bfc00014
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00014 to bfc00014
|
|
||||||
New PC from bfc00014 to bfc00018
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00018 to bfc00018
|
|
||||||
New PC from bfc00018 to bfc0001c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0001c to bfc0001c
|
|
||||||
New PC from bfc0001c to bfc00020
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00020 to bfc00020
|
|
||||||
New PC from bfc00020 to bfc00024
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00024 to bfc00024
|
|
||||||
New PC from bfc00024 to bfc00028
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00028 to bfc00028
|
|
||||||
New PC from bfc00028 to bfc0002c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0002c to bfc0002c
|
|
||||||
New PC from bfc0002c to bfc00030
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00030 to bfc00030
|
|
||||||
New PC from bfc00030 to bfc00034
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00034 to bfc00034
|
|
||||||
New PC from bfc00034 to bfc00038
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00038 to bfc00038
|
|
||||||
New PC from bfc00038 to bfc0003c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0003c to bfc0003c
|
|
||||||
Opcode: 00
|
|
||||||
CTRLREGDST: Rd
|
|
||||||
Memory read disabled
|
|
||||||
Opcode: xx
|
|
||||||
xxxxxxxxxxxxxx
|
|
||||||
New PC from bfc0003c to bfc00040
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00040 to bfc00040
|
|
||||||
New PC from bfc00040 to bfc00044
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00044 to bfc00044
|
|
||||||
New PC from bfc00044 to bfc00048
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00048 to bfc00048
|
|
||||||
New PC from bfc00048 to bfc0004c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0004c to bfc0004c
|
|
||||||
New PC from bfc0004c to bfc00050
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00050 to bfc00050
|
|
||||||
New PC from bfc00050 to bfc00054
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00054 to bfc00054
|
|
||||||
New PC from bfc00054 to bfc00058
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00058 to bfc00058
|
|
||||||
New PC from bfc00058 to bfc0005c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0005c to bfc0005c
|
|
||||||
New PC from bfc0005c to bfc00060
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00060 to bfc00060
|
|
||||||
New PC from bfc00060 to bfc00064
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00064 to bfc00064
|
|
||||||
New PC from bfc00064 to bfc00068
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00068 to bfc00068
|
|
||||||
New PC from bfc00068 to bfc0006c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0006c to bfc0006c
|
|
||||||
New PC from bfc0006c to bfc00070
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00070 to bfc00070
|
|
||||||
New PC from bfc00070 to bfc00074
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00074 to bfc00074
|
|
||||||
New PC from bfc00074 to bfc00078
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00078 to bfc00078
|
|
||||||
New PC from bfc00078 to bfc0007c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0007c to bfc0007c
|
|
||||||
New PC from bfc0007c to bfc00080
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00080 to bfc00080
|
|
||||||
New PC from bfc00080 to bfc00084
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00084 to bfc00084
|
|
||||||
New PC from bfc00084 to bfc00088
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00088 to bfc00088
|
|
||||||
New PC from bfc00088 to bfc0008c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0008c to bfc0008c
|
|
||||||
New PC from bfc0008c to bfc00090
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00090 to bfc00090
|
|
||||||
New PC from bfc00090 to bfc00094
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00094 to bfc00094
|
|
||||||
New PC from bfc00094 to bfc00098
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc00098 to bfc00098
|
|
||||||
New PC from bfc00098 to bfc0009c
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc0009c to bfc0009c
|
|
||||||
New PC from bfc0009c to bfc000a0
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000a0 to bfc000a0
|
|
||||||
New PC from bfc000a0 to bfc000a4
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000a4 to bfc000a4
|
|
||||||
New PC from bfc000a4 to bfc000a8
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000a8 to bfc000a8
|
|
||||||
New PC from bfc000a8 to bfc000ac
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000ac to bfc000ac
|
|
||||||
New PC from bfc000ac to bfc000b0
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000b0 to bfc000b0
|
|
||||||
New PC from bfc000b0 to bfc000b4
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000b4 to bfc000b4
|
|
||||||
New PC from bfc000b4 to bfc000b8
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000b8 to bfc000b8
|
|
||||||
New PC from bfc000b8 to bfc000bc
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000bc to bfc000bc
|
|
||||||
New PC from bfc000bc to bfc000c0
|
|
||||||
Reg File Write data: x
|
|
||||||
Reg File Write data: x
|
|
||||||
New PC from bfc000c0 to bfc000c0
|
|
||||||
New PC from bfc000c0 to bfc000c4
|
|
||||||
Reg File Write data: x
|
|
||||||
FATAL: testbench/mips_cpu_harvard_tb.v:47: Simulation did not finish within 100 cycles.
|
|
||||||
Time: 2000 Scope: mips_cpu_harvard_tb
|
|
||||||
|
|
@ -1 +0,0 @@
|
||||||
Time: 2000 Scope: mips_cpu_harvard_tb
|
|
||||||
1
inputs/beq.ref.txt
Normal file
1
inputs/beq.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -1,7 +1,8 @@
|
||||||
50004043
|
34040005
|
||||||
50005043
|
34050005
|
||||||
20005801
|
10850003
|
||||||
00006C42
|
00000000
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
00000008
|
||||||
1
inputs/bgez.ref.txt
Normal file
1
inputs/bgez.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -1,6 +1,7 @@
|
||||||
30004043
|
34040003
|
||||||
20001840
|
04810003
|
||||||
00006C42
|
00000000
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
00000008
|
||||||
1
inputs/bgezal.ref.txt
Normal file
1
inputs/bgezal.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
2
|
||||||
|
|
@ -1,7 +1,8 @@
|
||||||
30004043
|
34040003
|
||||||
30001940
|
04910004
|
||||||
00006C42
|
00000000
|
||||||
10002442
|
24420001
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
03E00008
|
||||||
1
inputs/bgtz.ref.txt
Normal file
1
inputs/bgtz.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -1,6 +1,7 @@
|
||||||
30004043
|
34040003
|
||||||
200008C1
|
1C800003
|
||||||
00006C42
|
00000000
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
00000008
|
||||||
|
|
|
||||||
1
inputs/blez.ref.txt
Normal file
1
inputs/blez.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -1,6 +1,7 @@
|
||||||
FFFF4043
|
3C05FFFF
|
||||||
20000881
|
18800003
|
||||||
00006C42
|
00000000
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
00000008
|
||||||
1
inputs/bltz.ref.txt
Normal file
1
inputs/bltz.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -1,6 +1,7 @@
|
||||||
FFFF4043
|
3C05FFFF
|
||||||
20000840
|
04800003
|
||||||
00006C42
|
00000000
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
00000008
|
||||||
1
inputs/bltzal.ref.txt
Normal file
1
inputs/bltzal.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
2
|
||||||
|
|
@ -1,7 +1,8 @@
|
||||||
FFFF4043
|
3C05FFFF
|
||||||
20000940
|
04900004
|
||||||
00006C42
|
00000000
|
||||||
10002442
|
24420001
|
||||||
80000000
|
00000000
|
||||||
10002043
|
00000008
|
||||||
80000000
|
34020001
|
||||||
|
03E00008
|
||||||
1
inputs/bne.ref.txt
Normal file
1
inputs/bne.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -1,7 +1,8 @@
|
||||||
30004043
|
34040003
|
||||||
50005043
|
34040005
|
||||||
20005841
|
14850003
|
||||||
00006C42
|
00000000
|
||||||
80000000
|
00000008
|
||||||
10002043
|
00000000
|
||||||
80000000
|
34020001
|
||||||
|
00000008
|
||||||
1
inputs/bqtz.ref.txt
Normal file
1
inputs/bqtz.ref.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
1
|
||||||
|
|
@ -20,13 +20,11 @@ module mips_cpu_harvard(
|
||||||
input logic[31:0] data_readdata//port from data memory out, going to the 'Write Register' port in regfile.
|
input logic[31:0] data_readdata//port from data memory out, going to the 'Write Register' port in regfile.
|
||||||
);
|
);
|
||||||
|
|
||||||
always_comb begin
|
assign instr_address = in_pc_in;
|
||||||
instr_address = in_pc_in;
|
assign data_address = out_ALURes;
|
||||||
data_address = out_ALURes;
|
assign data_write = out_MemWrite;
|
||||||
data_write = out_MemWrite;
|
assign data_read = out_MemRead;
|
||||||
data_read = out_MemRead;
|
assign data_writedata = out_readdata2;
|
||||||
data_writedata = out_readdata2;
|
|
||||||
end
|
|
||||||
|
|
||||||
logic[31:0] in_pc_in, out_pc_out = 32'hBFC00000, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata;
|
logic[31:0] in_pc_in, out_pc_out = 32'hBFC00000, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata;
|
||||||
logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp;
|
logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp;
|
||||||
|
|
@ -38,7 +36,7 @@ assign in_readreg1 = instr_readdata[25:21];
|
||||||
assign in_readreg2 = instr_readdata[20:16];
|
assign in_readreg2 = instr_readdata[20:16];
|
||||||
assign in_opcode = instr_readdata[31:26];
|
assign in_opcode = instr_readdata[31:26];
|
||||||
|
|
||||||
always_comb begin
|
always @(*) begin
|
||||||
//Picking what register should be written to.
|
//Picking what register should be written to.
|
||||||
case(out_RegDst)
|
case(out_RegDst)
|
||||||
2'd0: begin
|
2'd0: begin
|
||||||
|
|
@ -76,10 +74,12 @@ always_comb begin
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
pc pc(
|
mips_cpu_pc pc(
|
||||||
//PC inputs
|
//PC inputs
|
||||||
.clk(clk),//clk taken from the Standard signals
|
.clk(clk),//clk taken from the Standard signals
|
||||||
.rst(reset),//clk taken from the Standard signals
|
.rst(reset),//clk taken from the Standard signals
|
||||||
|
.instr(instr_readdata), //needed for branches and jumps
|
||||||
|
.reg_readdata(out_readdata1), //needed for jump register
|
||||||
.pc_ctrl(out_PC),
|
.pc_ctrl(out_PC),
|
||||||
.pc_in(out_pc_out),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
|
.pc_in(out_pc_out),//what the pc will output on the next clock cycle taken from either: PC itself + 4(Normal/Default Operation); or 16-bit signed valued taken from Instr[15-0] sign extend to 32bit then shifted by 2 then added to PC + 4(Branch Operation); or 26-bit instruction address taken from J-type instr[25-0] shifted left by 2 then concatanated to form Jump Address (PC-region branch); or from the GPR rs.
|
||||||
//PC outputs
|
//PC outputs
|
||||||
|
|
|
||||||
|
|
@ -1,45 +1,46 @@
|
||||||
module pc(
|
module mips_cpu_pc(
|
||||||
input logic clk,
|
input logic clk,
|
||||||
input logic rst,
|
input logic rst,
|
||||||
input logic[1:0] pc_ctrl,
|
input logic[1:0] pc_ctrl,
|
||||||
input logic[31:0] pc_in,
|
input logic[31:0] pc_in,
|
||||||
input logic[4:0] rs,
|
input logic[31:0] instr,
|
||||||
output logic[31:0] pc_out,
|
input logic[31:0] reg_readdata,
|
||||||
output logic active
|
output logic[31:0] pc_out,
|
||||||
|
output logic active
|
||||||
);
|
);
|
||||||
|
|
||||||
reg [31:0] pc_curr;
|
reg [31:0] pc_next, pc_lit_next;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
pc_out = pc_in;
|
pc_out = pc_in;
|
||||||
end // initial
|
pc_next = pc_out + 32'd4;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign pc_lit_next = pc_out + 32'd4;
|
||||||
|
|
||||||
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
||||||
if (rst) begin
|
if (rst) begin
|
||||||
active <= 1;
|
active <= 1;
|
||||||
pc_out <= 32'hBFC00000;
|
pc_out <= 32'hBFC00000;
|
||||||
end else if (pc_out != 32'd0) begin
|
end else begin
|
||||||
active <= active;
|
pc_out <= pc_next;
|
||||||
case(pc_ctrl)
|
case(pc_ctrl)
|
||||||
2'd0: begin
|
default: begin
|
||||||
pc_curr <= pc_out;
|
pc_next <= pc_out + 32'd4;
|
||||||
pc_out <= pc_curr + 32'd4;//No branch or jump or load, so no delay slot.
|
|
||||||
$display("New PC from %h to %h", pc_curr, pc_out);
|
|
||||||
end
|
end
|
||||||
2'd1: begin
|
2'd1: begin // Branch
|
||||||
pc_out <= pc_in;//Branches
|
pc_next <= pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00};
|
||||||
end
|
end
|
||||||
2'd2: begin
|
2'd2: begin // Jump
|
||||||
pc_out <= pc_in;//Jumps
|
pc_next <= {pc_lit_next[31:28], instr[25:0], 2'b00};
|
||||||
end
|
end
|
||||||
2'd3: begin
|
2'd3: begin // Jump using Register
|
||||||
$display("JUMP REGISTER");
|
pc_next <= reg_readdata;
|
||||||
pc_out <= 32'd0;//Jumps using register
|
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end else if (pc_out == 32'd0) begin
|
end
|
||||||
|
if (pc_out == 32'd0) begin
|
||||||
active <= 0;
|
active <= 0;
|
||||||
//$display("CPU Halt");
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,21 +1,44 @@
|
||||||
#!/bin/bash
|
#!/bin/bash
|
||||||
|
|
||||||
|
#arithmetic
|
||||||
bash test/test_mips_cpu_harvard.sh rtl addu #Pass
|
bash test/test_mips_cpu_harvard.sh rtl addu #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl addiu #Pass
|
bash test/test_mips_cpu_harvard.sh rtl addiu #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl ori #Pass
|
bash test/test_mips_cpu_harvard.sh rtl ori #Pass
|
||||||
#bash test/test_mips_cpu_harvard.sh rtl sw
|
|
||||||
bash test/test_mips_cpu_harvard.sh rtl and #Pass
|
bash test/test_mips_cpu_harvard.sh rtl and #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl andi #Pass
|
bash test/test_mips_cpu_harvard.sh rtl andi #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl or #Pass
|
bash test/test_mips_cpu_harvard.sh rtl or #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl xor #Pass
|
bash test/test_mips_cpu_harvard.sh rtl xor #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl xori #Pass
|
bash test/test_mips_cpu_harvard.sh rtl xori #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl sll
|
bash test/test_mips_cpu_harvard.sh rtl subu #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl slti
|
|
||||||
bash test/test_mips_cpu_harvard.sh rtl sltiu #Pass
|
|
||||||
|
#load & store
|
||||||
|
bash test/test_mips_cpu_harvard.sh rtl beq #Pass
|
||||||
|
bash test/test_mips_cpu_harvard.sh rtl bgez #Pass
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl bgezal
|
||||||
|
bash test/test_mips_cpu_harvard.sh rtl bgtz #Pass
|
||||||
|
bash test/test_mips_cpu_harvard.sh rtl blez #Pass
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl bltz
|
||||||
|
bash test/test_mips_cpu_harvard.sh rtl bltzal #Pass
|
||||||
|
bash test/test_mips_cpu_harvard.sh rtl bne #Pass
|
||||||
|
|
||||||
|
|
||||||
|
# shift
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl sll
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl srl
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl sra
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl srav
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl srlv
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl sw
|
||||||
|
|
||||||
|
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl slti
|
||||||
|
#bash test/test_mips_cpu_harvard.sh rtl sltiu
|
||||||
#bash test/test_mips_cpu_harvard.sh rtl slt # missing
|
#bash test/test_mips_cpu_harvard.sh rtl slt # missing
|
||||||
bash test/test_mips_cpu_harvard.sh rtl sltu #Pass
|
bash test/test_mips_cpu_harvard.sh rtl sltu #Pass
|
||||||
bash test/test_mips_cpu_harvard.sh rtl sra
|
|
||||||
bash test/test_mips_cpu_harvard.sh rtl srav
|
|
||||||
bash test/test_mips_cpu_harvard.sh rtl srl
|
|
||||||
bash test/test_mips_cpu_harvard.sh rtl srlv
|
|
||||||
bash test/test_mips_cpu_harvard.sh rtl subu #Pass
|
|
||||||
|
|
|
||||||
|
|
@ -51,7 +51,7 @@ iverilog -Wall -g2012 \
|
||||||
-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
|
-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
|
||||||
-P mips_cpu_harvard_tb.MEM_INIT_FILE=\"inputs/${INSTR}.data.txt\" \
|
-P mips_cpu_harvard_tb.MEM_INIT_FILE=\"inputs/${INSTR}.data.txt\" \
|
||||||
-o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
|
-o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
|
||||||
${SRC} #2> /dev/null
|
${SRC} 2> /dev/null
|
||||||
/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR} &> ./inputs/${INSTR}.log.txt; # log file for debugging (contains $display)
|
/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR} &> ./inputs/${INSTR}.log.txt; # log file for debugging (contains $display)
|
||||||
echo "$(tail -1 ./inputs/${INSTR}.log.txt)" > ./inputs/${INSTR}.out.txt; # register v0 output to compare with reference
|
echo "$(tail -1 ./inputs/${INSTR}.log.txt)" > ./inputs/${INSTR}.out.txt; # register v0 output to compare with reference
|
||||||
if diff -w ./inputs/${INSTR}.out.txt ./inputs/${INSTR}.ref.txt &> /dev/null # compare
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if diff -w ./inputs/${INSTR}.out.txt ./inputs/${INSTR}.ref.txt &> /dev/null # compare
|
||||||
|
|
|
||||||
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Reference in a new issue