ELEC50010-IAC-CW/rtl/mips_cpu_alu.v

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module mips_cpu_alu(
input logic clk, //clock for special registers Hi and Lo
input logic rst,
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input logic[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs.
input logic[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt. Or from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0].
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input logic [4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
input logic [4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from GPR rs (Variable)
input logic[31:0] Hi_in,
input logic[31:0] Lo_in,
input logic SpcRegWriteEn,
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output logic ALUCond, //If a relevant condition is met, this output goes high(Active High). Note: Relevant as in related to current condition being tested.
output logic[31:0] ALURes, // The ouput of the ALU
output logic[31:0] ALUHi, //Special Hi Register output
output logic[31:0] ALULo //Special Hi Register output
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);
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/*
Alu Operations:
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-Manipulation Operations: They perform an operation on a value(s) and have an output to ALURes.
- Addition (unsigned)
- Subtraction (unsigned)
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- Multiplication
- Division
- Bitwise AND
- Bitwise OR
- Bitwise XOR
- Shift Left Logical
- Shift Left Logical Variable
- Shift Right Logical
- Shift Right Logical Variable
- Shift Right Arithmetic
- Shift Right Arithmetic Variable
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- Set On Less Than (signed)
- Set On Less Than Unsigned
- Multiplication (unsigned)
- Division (unsigned)
-Condtional Check Operations: They check conditions and have an output to ALUCond
- Equality (=) (signed)
- Less Than (<) (signed)
- Less Than or Equal To (<=) (signed)
- Greater Than (>) (signed)
- Greater Than or Equal to (>=) (signed)
- Negative Equality(=/=) (signed)
-Implementation Operation: A design choice used for implmentation.
- MTHI (move the contents of GPR rs to special register Hi)
- MTLO (move the contents of GPR rs to special register Lo)
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*/
typedef enum logic [4:0]{ //Enum list to use words instead of numbers when refering to operations.
ADD = 5'd0,
SUB = 5'd1,
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MUL = 5'd2,//signed multiply
DIV = 5'd3,//signed divide
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AND = 5'd4,
OR = 5'd5,
XOR = 5'd6,
SLL = 5'd7,
SLLV = 5'd8,
SRL = 5'd9,
SRLV = 5'd10,
SRA = 5'd11,
SRAV = 5'd12,
EQ = 5'd13,
LES = 5'd14,
LEQ = 5'd15,
GRT = 5'd16,
GEQ = 5'd17,
NEQ = 5'd18,
// PAS = 5'd19, no need for PAS as it was based on faulty reasoning that speical registers Hi and Lo are in the reg file.
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SLT = 5'd20,//signed compare
SLTU = 5'd21,//unsigned compare
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MULU = 5'd22,//unsigned multiply
DIVU = 5'd23,//unsigned divide
MTHI = 5'd24,
MTLO = 5'd25
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} Ops;
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Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation.
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logic signed[63:0] SMulRes;//signed result of multiplication.
logic[63:0] UMulRes;//unsigned result of multiplication.
logic[31:0] temp_Hi;
logic[31:0] temp_Lo;
reg [31:0] Hi;
reg [31:0] Lo;
assign ALUHi = Hi;//combinatorial read of Hi register
assign ALULo = Lo;//combinatorial read of Lo register
initial begin
Hi <= 32'd0;
Lo <= 32'd0;
end
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always @(*) begin
assign ALUOps = ALUOp;
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case(ALUOps)
ADD: begin
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ALURes = $signed(A) + $signed(B);
end
SUB: begin
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ALURes = $signed(A) - $signed(B);
end
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MUL: begin
SMulRes = $signed(A) * $signed(B);
temp_Hi = SMulRes[63:32];
temp_Lo = SMulRes[31:0];
end
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DIV: begin
temp_Lo = $signed(A) / $signed(B);
temp_Hi = $signed(A) % $signed(B);
end
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AND: begin
ALURes = A & B;
end
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OR: begin
ALURes = A | B;
end
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XOR: begin
ALURes = A^B;
end
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SLL: begin
ALURes = B << shamt;
$display("ALURES SLL: %h", ALURes);
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end
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SLLV: begin
ALURes = B << A;
end
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SRL: begin
ALURes = B >> shamt;
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end
SRLV: begin
ALURes = B >> A;
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end
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SRA: begin
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ALURes = $signed(B) >>> shamt;
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end
SRAV: begin
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ALURes = $signed(B) >>> A;
end
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EQ: begin
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if ($signed(A) == $signed(B)) begin
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ALUCond = 1;
end
else begin
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ALUCond = 0;
end
end
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LES: begin
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$display("ALU A: %h B: %h", $signed(A), $signed(B));
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if ($signed(A) < $signed(B)) begin
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ALUCond = 1;
end
else begin
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ALUCond = 0;
end
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end
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LEQ: begin
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if ($signed(A) <= $signed(B)) begin
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ALUCond = 1;
end
else begin
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ALUCond = 0;
end
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end
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GRT: begin
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if ($signed(A) > $signed(B)) begin
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ALUCond = 1;
end
else begin
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ALUCond = 0;
end
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end
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GEQ: begin
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if ($signed(A) >= $signed(B)) begin
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ALUCond = 1;
end
else begin
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ALUCond = 0;
end
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end
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NEQ: begin
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if ($signed(A) != $signed(B)) begin
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ALUCond = 1;
end
else begin
ALUCond = 0;
end
end
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/*
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PAS: begin
ALURes = A;
end
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*/
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SLT: begin
if ($signed(A) < $signed(B)) begin
ALURes = 1;
end
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else begin
ALURes = 0;
end
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end
SLTU: begin
if (A < B) begin
ALURes = 1;
end
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else begin
ALURes = 0;
end
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end
MULU: begin
UMulRes = A * B;
temp_Hi = UMulRes[63:32];
temp_Lo = UMulRes[31:0];
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end
DIVU: begin
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$display("ALU A: %h B: %h", A, B);
temp_Lo = A / B;
temp_Hi = A % B;
end
MTHI: begin
temp_Hi = Hi_in;
end
MTLO: begin
temp_Lo = Lo_in;
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end
endcase
end
always_ff @(posedge clk) begin
if(rst)begin
Hi <= 0;
Lo <= 0;
end else if (SpcRegWriteEn) begin
Hi <= temp_Hi;
Lo <= temp_Lo;
end
end
endmodule