10 commits

Author	SHA1	Message	Date
Kacper	5dd725f7bf	Brought up to date with Pipelined	2020-06-14 15:47:34 +01:00
Aadi Desai	6c1f7fc59b	Remove debug lines from ALU to improve performance	2020-06-11 16:23:16 +01:00
Aadi Desai	a1cf89e644	Added LDR and STR to alu and set up data paths ... Decoder changes remaining	2020-06-10 14:02:15 +01:00
Aadi Desai	fefcad13ce	Updated alu to feed only positive values to multiply block ... When both values are positive/negative the positive result from the multiply block is correct. When only one is negative, the result is inverted.	2020-06-09 20:34:29 +01:00
Aadi Desai	f6b3489884	Updated ALU to include PSH and POP	2020-06-04 18:12:24 +01:00
Kacper	4318a5b70b	CPU completed	2020-06-04 16:33:27 +01:00
Aadi Desai	08a8635959	Updated ALU to use internal carry register ... Also tidied up begin/end tags to reduce number of lines and improve readability	2020-06-04 15:05:13 +01:00
Aadi Desai	3647e0b15c	ALU now uses multiply block rather than * operator ... Updated to use custom block and decide which step of MUL, MLA and MLS depending on exec2 input	2020-06-03 15:15:44 +01:00
Aadi Desai	2ca1e90a2c	ALU enable control added, minor fix with RRC ... Multiply still to be updated	2020-06-02 16:57:58 +01:00
Aadi Desai	3f0c91b0ff	Initial ALU Verilog ... Currently using incorrect implementation for Multiply (* operator), to be fixed once Multiply method is decided	2020-05-29 14:16:02 +01:00