supleed2/ELEC40006-P1-CW
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32 commits 1 branch 0 tags 69 MiB
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11 commits

Author SHA1 Message Date
Kacper 9a1a1da664 Complete CPU v2 (not tested) 2020-06-07 16:12:05 +01:00
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00
Kacper 4318a5b70b CPU completed 2020-06-04 16:33:27 +01:00
Kacper 1c0032fa95 Fixed decoder and SM 2020-06-02 20:09:22 +01:00
Kacper cf179ad2cf Revisions for testing 2020-05-27 18:53:59 +01:00
Kacper e1acb56b66 Finished decoder 2020-05-27 18:53:03 +01:00
Kacper 5ed70dabb0 Working on datapath 2020-05-27 11:10:13 +01:00
Kacper 3b298e02a2 Finished datapath 2020-05-25 18:00:34 +01:00
Kacper 6b2363d6a1 Working on initial design 2020-05-25 17:16:24 +01:00
Benjamin 14418c8725 VCS Test 2020-05-20 19:24:20 +01:00
Aadi Desai 26c28a829d Basic Project Setup 2020-05-20 12:44:57 +01:00