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112
system_template_de1_soc/Cordic_Impl1.v
Normal file
112
system_template_de1_soc/Cordic_Impl1.v
Normal file
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@ -0,0 +1,112 @@
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module Cordic_Impl1(
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input clk,
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input clk_en,
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input start,
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input reset,
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input [31:0] dataa,
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output [31:0] result,
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output [31:0] z_debug,
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output [31:0] angle_debug,
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output [4:0] iter_debug,
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output done,
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output [31:0] y_debug
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);
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reg [31:0] x_out,y_out,z_out;
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reg [31:0] x_next,y_next,z_next;
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reg [4:0] iter,iter_next;
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wire [31:0] angle_lut [31:0];
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reg working, working_next;
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assign z_debug = z_out;
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assign result = x_out;
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assign angle_debug = angle_lut[iter];
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assign y_debug = y_out;
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assign iter_debug = iter;
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assign done = (iter==5'b11111);
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always@(posedge clk or posedge reset) begin
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if(reset) begin
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x_out <= 0;
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y_out <= 0;
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z_out <= 0;
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iter <= 0;
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working <= 0;
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end else begin
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x_out <= x_next;
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y_out <= y_next;
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z_out <= z_next;
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if(done) begin
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working <= 0;
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end else begin
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working <= working_next;
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end
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iter <= iter_next;
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end
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end
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always @(*) begin
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if(working) begin
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if(~z_out[31]) begin
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x_next <= x_out - ({{32{y_out[31]}}, y_out} >> iter);
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y_next <= y_out + ({{32{x_out[31]}}, x_out} >> iter);
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z_next <= z_out - angle_lut[iter];
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end
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else begin
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x_next <= x_out + ({{32{y_out[31]}}, y_out} >> iter);
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y_next <= y_out - ({{32{x_out[31]}}, x_out} >> iter);
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z_next <= z_out + angle_lut[iter];
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end
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iter_next <= iter+1;
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end
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else if(start) begin
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x_next <= 32'b00100110110111010011101101101010; //Gain factor
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y_next <= 0;
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z_next <= dataa;
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working_next <= 1;
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iter_next <= 0;
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end else begin
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x_next <= 0;
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y_next <= 0;
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z_next <= 0;
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working_next <= 0;
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iter_next <= 0;
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end
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end
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assign angle_lut[0] = 32'b00110010010000111111011010101000;
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assign angle_lut[1] = 32'b00011101101011000110011100000101;
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assign angle_lut[2] = 32'b00001111101011011011101011111100;
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assign angle_lut[3] = 32'b00000111111101010110111010100110;
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assign angle_lut[4] = 32'b00000011111111101010101101110110;
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assign angle_lut[5] = 32'b00000001111111111101010101011011;
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assign angle_lut[6] = 32'b00000000111111111111101010101010;
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assign angle_lut[7] = 32'b00000000011111111111111101010101;
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assign angle_lut[8] = 32'b00000000001111111111111111101010;
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assign angle_lut[9] = 32'b00000000000111111111111111111101;
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assign angle_lut[10] = 32'b00000000000011111111111111111111;
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assign angle_lut[11] = 32'b00000000000001111111111111111111;
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assign angle_lut[12] = 32'b00000000000000111111111111111111;
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assign angle_lut[13] = 32'b00000000000000011111111111111111;
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assign angle_lut[14] = 32'b00000000000000001111111111111111;
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assign angle_lut[15] = 32'b00000000000000000111111111111111;
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assign angle_lut[16] = 32'b00000000000000000011111111111111;
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assign angle_lut[17] = 32'b00000000000000000010000000000000;
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assign angle_lut[18] = 32'b00000000000000000000111111111111;
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assign angle_lut[19] = 32'b00000000000000000000100000000000;
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assign angle_lut[20] = 32'b00000000000000000000001111111111;
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assign angle_lut[21] = 32'b00000000000000000000000111111111;
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assign angle_lut[22] = 32'b00000000000000000000000100000000;
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assign angle_lut[23] = 32'b00000000000000000000000001111111;
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assign angle_lut[24] = 32'b00000000000000000000000001000000;
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assign angle_lut[25] = 32'b00000000000000000000000000011111;
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assign angle_lut[26] = 32'b00000000000000000000000000001111;
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assign angle_lut[27] = 32'b00000000000000000000000000001000;
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assign angle_lut[28] = 32'b00000000000000000000000000000011;
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assign angle_lut[29] = 32'b00000000000000000000000000000010;
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assign angle_lut[30] = 32'b00000000000000000000000000000000;
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assign angle_lut[31] = 32'b00000000000000000000000000000000;
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endmodule
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5
system_template_de1_soc/const128.v
Normal file
5
system_template_de1_soc/const128.v
Normal file
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@ -0,0 +1,5 @@
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module const128 (
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output [31:0] result
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);
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assign result = 32'b01000011000000000000000000000000;
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endmodule
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110
system_template_de1_soc/cordic.v
Normal file
110
system_template_de1_soc/cordic.v
Normal file
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@ -0,0 +1,110 @@
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module cordic(
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input clk,
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input clk_en,
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input start,
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input reset,
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input [31:0] dataa,
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output [31:0] result,
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output done
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);
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parameter [4:0] stages = 16;
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reg [31:0] x_out,y_out,z_out;
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reg [31:0] x_next,y_next,z_next;
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reg [4:0] iter,iter_next;
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wire [31:0] angle_lut [31:0];
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reg working, working_next;
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assign z_debug = z_out;
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assign result = x_out;
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assign angle_debug = angle_lut[iter];
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assign y_debug = y_out;
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assign iter_debug = iter;
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assign done = (iter==stages);
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always@(posedge clk or posedge reset) begin
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if(reset) begin
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x_out <= 0;
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y_out <= 0;
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z_out <= 0;
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iter <= 0;
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working <= 0;
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end else begin
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x_out <= x_next;
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y_out <= y_next;
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z_out <= z_next;
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if(done) begin
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working <= 0;
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end else begin
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working <= working_next;
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end
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iter <= iter_next;
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end
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end
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always @(*) begin
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if(working) begin
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if(~z_out[31]) begin
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x_next <= x_out - ({{32{y_out[31]}}, y_out} >> iter);
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y_next <= y_out + ({{32{x_out[31]}}, x_out} >> iter);
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z_next <= z_out - angle_lut[iter];
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end
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else begin
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x_next <= x_out + ({{32{y_out[31]}}, y_out} >> iter);
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y_next <= y_out - ({{32{x_out[31]}}, x_out} >> iter);
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z_next <= z_out + angle_lut[iter];
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end
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iter_next <= iter+1;
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end
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else if(start) begin
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x_next <= 32'b00100110110111010011101101101010; //Gain factor
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y_next <= 0;
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z_next <= dataa;
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working_next <= 1;
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iter_next <= 0;
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end else begin
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x_next <= 0;
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y_next <= 0;
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z_next <= 0;
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working_next <= 0;
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iter_next <= 0;
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end
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end
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assign angle_lut[0] = 32'b00110010010000111111011010101001;
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assign angle_lut[1] = 32'b00011101101011000110011100000101;
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assign angle_lut[2] = 32'b00001111101011011011101011111101;
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assign angle_lut[3] = 32'b00000111111101010110111010100111;
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assign angle_lut[4] = 32'b00000011111111101010101101110111;
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assign angle_lut[5] = 32'b00000001111111111101010101011100;
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assign angle_lut[6] = 32'b00000000111111111111101010101011;
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assign angle_lut[7] = 32'b00000000011111111111111101010101;
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assign angle_lut[8] = 32'b00000000001111111111111111101011;
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assign angle_lut[9] = 32'b00000000000111111111111111111101;
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assign angle_lut[10] = 32'b00000000000100000000000000000000;
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assign angle_lut[11] = 32'b00000000000010000000000000000000;
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assign angle_lut[12] = 32'b00000000000001000000000000000000;
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assign angle_lut[13] = 32'b00000000000000100000000000000000;
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assign angle_lut[14] = 32'b00000000000000010000000000000000;
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assign angle_lut[15] = 32'b00000000000000001000000000000000;
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assign angle_lut[16] = 32'b00000000000000000100000000000000;
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assign angle_lut[17] = 32'b00000000000000000010000000000000;
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assign angle_lut[18] = 32'b00000000000000000001000000000000;
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assign angle_lut[19] = 32'b00000000000000000000100000000000;
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assign angle_lut[20] = 32'b00000000000000000000010000000000;
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assign angle_lut[21] = 32'b00000000000000000000001000000000;
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assign angle_lut[22] = 32'b00000000000000000000000100000000;
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assign angle_lut[23] = 32'b00000000000000000000000010000000;
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assign angle_lut[24] = 32'b00000000000000000000000001000000;
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assign angle_lut[25] = 32'b00000000000000000000000000100000;
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assign angle_lut[26] = 32'b00000000000000000000000000010000;
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assign angle_lut[27] = 32'b00000000000000000000000000001000;
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assign angle_lut[28] = 32'b00000000000000000000000000000100;
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assign angle_lut[29] = 32'b00000000000000000000000000000010;
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assign angle_lut[30] = 32'b00000000000000000000000000000001;
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assign angle_lut[31] = 32'b00000000000000000000000000000001;
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endmodule
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73
system_template_de1_soc/cordic_t.v
Normal file
73
system_template_de1_soc/cordic_t.v
Normal file
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@ -0,0 +1,73 @@
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module cordic_t(
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input clk,
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input clk_en,
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input reset,
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input [31:0] dataa,
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output [31:0] result
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);
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reg [31:0] x[16:0];
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reg [31:0] y[16:0];
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reg [31:0] z[16:0];
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integer i;
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wire [31:0] angle_lut [31:0];
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assign result = x[16];
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always @(*) begin
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if(reset) begin
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for(i = 0 ;i < 17; i = i+1) begin
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x[i] <= 0;
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y[i] <= 0;
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z[i] <= 0;
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end
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end else begin
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x[0] <= 32'b00100110110111010011101101101010;
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y[0] <= 0;
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z[0] <= dataa;
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for(i = 0 ;i < 16; i = i+1) begin
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if(~z[i][31]) begin
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x[i+1] <= x[i] - ({{32{y[i][31]}}, y[i]} >> i);
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y[i+1] <= y[i] + ({{32{x[i][31]}}, x[i]} >> i);
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z[i+1] <= z[i] - angle_lut[i];
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end
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else begin
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x[i+1] <= x[i] + ({{32{y[i][31]}}, y[i]} >> i);
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y[i+1] <= y[i] - ({{32{x[i][31]}}, x[i]} >> i);
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z[i+1] <= z[i] + angle_lut[i];
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end
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end
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end
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end
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assign angle_lut[0] = 32'b00110010010000111111011010101001;
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assign angle_lut[1] = 32'b00011101101011000110011100000101;
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assign angle_lut[2] = 32'b00001111101011011011101011111101;
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assign angle_lut[3] = 32'b00000111111101010110111010100111;
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assign angle_lut[4] = 32'b00000011111111101010101101110111;
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assign angle_lut[5] = 32'b00000001111111111101010101011100;
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assign angle_lut[6] = 32'b00000000111111111111101010101011;
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assign angle_lut[7] = 32'b00000000011111111111111101010101;
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assign angle_lut[8] = 32'b00000000001111111111111111101011;
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assign angle_lut[9] = 32'b00000000000111111111111111111101;
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assign angle_lut[10] = 32'b00000000000100000000000000000000;
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assign angle_lut[11] = 32'b00000000000010000000000000000000;
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assign angle_lut[12] = 32'b00000000000001000000000000000000;
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assign angle_lut[13] = 32'b00000000000000100000000000000000;
|
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assign angle_lut[14] = 32'b00000000000000010000000000000000;
|
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assign angle_lut[15] = 32'b00000000000000001000000000000000;
|
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assign angle_lut[16] = 32'b00000000000000000100000000000000;
|
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assign angle_lut[17] = 32'b00000000000000000010000000000000;
|
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assign angle_lut[18] = 32'b00000000000000000001000000000000;
|
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assign angle_lut[19] = 32'b00000000000000000000100000000000;
|
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assign angle_lut[20] = 32'b00000000000000000000010000000000;
|
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assign angle_lut[21] = 32'b00000000000000000000001000000000;
|
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assign angle_lut[22] = 32'b00000000000000000000000100000000;
|
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assign angle_lut[23] = 32'b00000000000000000000000010000000;
|
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assign angle_lut[24] = 32'b00000000000000000000000001000000;
|
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assign angle_lut[25] = 32'b00000000000000000000000000100000;
|
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assign angle_lut[26] = 32'b00000000000000000000000000010000;
|
||||
assign angle_lut[27] = 32'b00000000000000000000000000001000;
|
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assign angle_lut[28] = 32'b00000000000000000000000000000100;
|
||||
assign angle_lut[29] = 32'b00000000000000000000000000000010;
|
||||
assign angle_lut[30] = 32'b00000000000000000000000000000001;
|
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assign angle_lut[31] = 32'b00000000000000000000000000000001;
|
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endmodule
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122
system_template_de1_soc/dualfunction.v
Normal file
122
system_template_de1_soc/dualfunction.v
Normal file
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|
@ -0,0 +1,122 @@
|
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
// CREATED "Tue Mar 22 14:47:05 2022"
|
||||
|
||||
module dualfunction(
|
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clk,
|
||||
reset,
|
||||
en,
|
||||
start,
|
||||
dataa,
|
||||
datab,
|
||||
done,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire reset;
|
||||
input wire en;
|
||||
input wire start;
|
||||
input wire [31:0] dataa;
|
||||
input wire [31:0] datab;
|
||||
output reg done;
|
||||
output wire [31:0] result;
|
||||
|
||||
wire [31:0] SYNTHESIZED_WIRE_0;
|
||||
wire [31:0] SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
reg DFF_inst4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = 1;
|
||||
|
||||
|
||||
|
||||
|
||||
fullfunction b2v_inst(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.en(en),
|
||||
.start(start),
|
||||
.dataa(dataa),
|
||||
.done(SYNTHESIZED_WIRE_2),
|
||||
.result(SYNTHESIZED_WIRE_0));
|
||||
|
||||
|
||||
fullfunction b2v_inst1(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.en(en),
|
||||
.start(start),
|
||||
.dataa(datab),
|
||||
.done(SYNTHESIZED_WIRE_3),
|
||||
.result(SYNTHESIZED_WIRE_1));
|
||||
|
||||
|
||||
fp_add b2v_inst2(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_0),
|
||||
.b(SYNTHESIZED_WIRE_1),
|
||||
.q(result));
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_3;
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
DFF_inst4 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
DFF_inst4 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_inst4 <= SYNTHESIZED_WIRE_5;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
done <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
done <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
done <= DFF_inst4;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
122
system_template_de1_soc/dualfunction_t.v
Normal file
122
system_template_de1_soc/dualfunction_t.v
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
// CREATED "Sun Mar 27 15:17:39 2022"
|
||||
|
||||
module dualfunction_t(
|
||||
clk,
|
||||
reset,
|
||||
en,
|
||||
start,
|
||||
dataa,
|
||||
datab,
|
||||
done,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire reset;
|
||||
input wire en;
|
||||
input wire start;
|
||||
input wire [31:0] dataa;
|
||||
input wire [31:0] datab;
|
||||
output reg done;
|
||||
output wire [31:0] result;
|
||||
|
||||
wire [31:0] SYNTHESIZED_WIRE_0;
|
||||
wire [31:0] SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
reg DFF_inst4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = 1;
|
||||
|
||||
|
||||
|
||||
|
||||
fullfunction_t b2v_inst(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.en(en),
|
||||
.start(start),
|
||||
.dataa(dataa),
|
||||
.done(SYNTHESIZED_WIRE_2),
|
||||
.result(SYNTHESIZED_WIRE_0));
|
||||
|
||||
|
||||
fullfunction_t b2v_inst1(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.en(en),
|
||||
.start(start),
|
||||
.dataa(datab),
|
||||
.done(SYNTHESIZED_WIRE_3),
|
||||
.result(SYNTHESIZED_WIRE_1));
|
||||
|
||||
|
||||
fp_add b2v_inst2(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_0),
|
||||
.b(SYNTHESIZED_WIRE_1),
|
||||
.q(result));
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_3;
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
DFF_inst4 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
DFF_inst4 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_inst4 <= SYNTHESIZED_WIRE_5;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
done <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
done <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
done <= DFF_inst4;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because one or more lines are too long
92
system_template_de1_soc/fix_to_fp.v
Normal file
92
system_template_de1_soc/fix_to_fp.v
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
|
||||
// GENERATION: XML
|
||||
// fix_to_fp.v
|
||||
|
||||
// Generated using ACDS version 20.1 720
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module fix_to_fp (
|
||||
input wire clk, // clk.clk
|
||||
input wire areset, // areset.reset
|
||||
input wire [0:0] en, // en.en
|
||||
input wire [31:0] a, // a.a
|
||||
output wire [31:0] q // q.q
|
||||
);
|
||||
|
||||
fix_to_fp_0002 fix_to_fp_inst (
|
||||
.clk (clk), // clk.clk
|
||||
.areset (areset), // areset.reset
|
||||
.en (en), // en.en
|
||||
.a (a), // a.a
|
||||
.q (q) // q.q
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2022 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
|
||||
// Retrieval info: <generic name="FUNCTION_FAMILY" value="CONVERT" />
|
||||
// Retrieval info: <generic name="ARITH_function" value="ADD" />
|
||||
// Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
|
||||
// Retrieval info: <generic name="ALL_function" value="ADD" />
|
||||
// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
|
||||
// Retrieval info: <generic name="TRIG_function" value="SIN" />
|
||||
// Retrieval info: <generic name="COMPARE_function" value="MIN" />
|
||||
// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
|
||||
// Retrieval info: <generic name="fp_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_man" value="23" />
|
||||
// Retrieval info: <generic name="exponent_width" value="23" />
|
||||
// Retrieval info: <generic name="frequency_target" value="50" />
|
||||
// Retrieval info: <generic name="latency_target" value="2" />
|
||||
// Retrieval info: <generic name="performance_goal" value="combined" />
|
||||
// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
|
||||
// Retrieval info: <generic name="faithful_rounding" value="false" />
|
||||
// Retrieval info: <generic name="gen_enable" value="true" />
|
||||
// Retrieval info: <generic name="divide_type" value="0" />
|
||||
// Retrieval info: <generic name="select_signal_enable" value="false" />
|
||||
// Retrieval info: <generic name="scale_by_pi" value="false" />
|
||||
// Retrieval info: <generic name="number_of_inputs" value="2" />
|
||||
// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
|
||||
// Retrieval info: <generic name="report_resources_to_xml" value="false" />
|
||||
// Retrieval info: <generic name="fxpt_width" value="32" />
|
||||
// Retrieval info: <generic name="fxpt_fraction" value="30" />
|
||||
// Retrieval info: <generic name="fxpt_sign" value="1" />
|
||||
// Retrieval info: <generic name="fp_out_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_out_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_out_man" value="23" />
|
||||
// Retrieval info: <generic name="fp_in_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_in_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_in_man" value="23" />
|
||||
// Retrieval info: <generic name="enable_hard_fp" value="true" />
|
||||
// Retrieval info: <generic name="manual_dsp_planning" value="true" />
|
||||
// Retrieval info: <generic name="forceRegisters" value="1111" />
|
||||
// Retrieval info: <generic name="selected_device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="selected_device_speedgrade" value="7" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : fix_to_fp.vo
|
||||
// RELATED_FILES: fix_to_fp.v, dspba_library_package.vhd, dspba_library.vhd, fix_to_fp_0002.vhd
|
||||
8
system_template_de1_soc/fp_div128.v
Normal file
8
system_template_de1_soc/fp_div128.v
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
module fp_div128 (
|
||||
input [31:0] dataa,
|
||||
output [31:0] result
|
||||
);
|
||||
wire [7:0] NewExp;
|
||||
assign NewExp = dataa[30:23]-7;
|
||||
assign result = (dataa[30:23]<=6) ? 0 : {dataa[31],NewExp,dataa[22:0]};
|
||||
endmodule
|
||||
8
system_template_de1_soc/fp_div2.v
Normal file
8
system_template_de1_soc/fp_div2.v
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
module fp_div2 (
|
||||
input [31:0] dataa,
|
||||
output [31:0] result
|
||||
);
|
||||
wire [7:0] NewExp;
|
||||
assign NewExp = dataa[30:23]-1;
|
||||
assign result = (dataa[30:23]==0) ? 0 : {dataa[31],NewExp,dataa[22:0]};
|
||||
endmodule
|
||||
94
system_template_de1_soc/fp_sum.v
Normal file
94
system_template_de1_soc/fp_sum.v
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
|
||||
// GENERATION: XML
|
||||
// fp_sum.v
|
||||
|
||||
// Generated using ACDS version 20.1 720
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module fp_sum (
|
||||
input wire clk, // clk.clk
|
||||
input wire areset, // areset.reset
|
||||
input wire [0:0] en, // en.en
|
||||
input wire [31:0] a, // a.a
|
||||
input wire [31:0] b, // b.b
|
||||
output wire [31:0] q // q.q
|
||||
);
|
||||
|
||||
fp_sum_0002 fp_sum_inst (
|
||||
.clk (clk), // clk.clk
|
||||
.areset (areset), // areset.reset
|
||||
.en (en), // en.en
|
||||
.a (a), // a.a
|
||||
.b (b), // b.b
|
||||
.q (q) // q.q
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2022 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
|
||||
// Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
|
||||
// Retrieval info: <generic name="ARITH_function" value="ADD" />
|
||||
// Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
|
||||
// Retrieval info: <generic name="ALL_function" value="ADD" />
|
||||
// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
|
||||
// Retrieval info: <generic name="TRIG_function" value="SIN" />
|
||||
// Retrieval info: <generic name="COMPARE_function" value="MIN" />
|
||||
// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
|
||||
// Retrieval info: <generic name="fp_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_man" value="23" />
|
||||
// Retrieval info: <generic name="exponent_width" value="23" />
|
||||
// Retrieval info: <generic name="frequency_target" value="50" />
|
||||
// Retrieval info: <generic name="latency_target" value="2" />
|
||||
// Retrieval info: <generic name="performance_goal" value="combined" />
|
||||
// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
|
||||
// Retrieval info: <generic name="faithful_rounding" value="false" />
|
||||
// Retrieval info: <generic name="gen_enable" value="true" />
|
||||
// Retrieval info: <generic name="divide_type" value="0" />
|
||||
// Retrieval info: <generic name="select_signal_enable" value="false" />
|
||||
// Retrieval info: <generic name="scale_by_pi" value="false" />
|
||||
// Retrieval info: <generic name="number_of_inputs" value="2" />
|
||||
// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
|
||||
// Retrieval info: <generic name="report_resources_to_xml" value="false" />
|
||||
// Retrieval info: <generic name="fxpt_width" value="32" />
|
||||
// Retrieval info: <generic name="fxpt_fraction" value="0" />
|
||||
// Retrieval info: <generic name="fxpt_sign" value="1" />
|
||||
// Retrieval info: <generic name="fp_out_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_out_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_out_man" value="23" />
|
||||
// Retrieval info: <generic name="fp_in_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_in_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_in_man" value="23" />
|
||||
// Retrieval info: <generic name="enable_hard_fp" value="true" />
|
||||
// Retrieval info: <generic name="manual_dsp_planning" value="true" />
|
||||
// Retrieval info: <generic name="forceRegisters" value="1111" />
|
||||
// Retrieval info: <generic name="selected_device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="selected_device_speedgrade" value="7" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : fp_sum.vo
|
||||
// RELATED_FILES: fp_sum.v, dspba_library_package.vhd, dspba_library.vhd, fp_sum_0002.vhd
|
||||
92
system_template_de1_soc/fp_to_fix.v
Normal file
92
system_template_de1_soc/fp_to_fix.v
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
|
||||
// GENERATION: XML
|
||||
// fp_to_fix.v
|
||||
|
||||
// Generated using ACDS version 20.1 720
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module fp_to_fix (
|
||||
input wire clk, // clk.clk
|
||||
input wire areset, // areset.reset
|
||||
input wire [0:0] en, // en.en
|
||||
input wire [31:0] a, // a.a
|
||||
output wire [31:0] q // q.q
|
||||
);
|
||||
|
||||
fp_to_fix_0002 fp_to_fix_inst (
|
||||
.clk (clk), // clk.clk
|
||||
.areset (areset), // areset.reset
|
||||
.en (en), // en.en
|
||||
.a (a), // a.a
|
||||
.q (q) // q.q
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2022 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
|
||||
// Retrieval info: <generic name="FUNCTION_FAMILY" value="CONVERT" />
|
||||
// Retrieval info: <generic name="ARITH_function" value="ADD" />
|
||||
// Retrieval info: <generic name="CONVERT_function" value="FP_FXP" />
|
||||
// Retrieval info: <generic name="ALL_function" value="ADD" />
|
||||
// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
|
||||
// Retrieval info: <generic name="TRIG_function" value="SIN" />
|
||||
// Retrieval info: <generic name="COMPARE_function" value="MIN" />
|
||||
// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
|
||||
// Retrieval info: <generic name="fp_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_man" value="23" />
|
||||
// Retrieval info: <generic name="exponent_width" value="23" />
|
||||
// Retrieval info: <generic name="frequency_target" value="50" />
|
||||
// Retrieval info: <generic name="latency_target" value="1" />
|
||||
// Retrieval info: <generic name="performance_goal" value="combined" />
|
||||
// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
|
||||
// Retrieval info: <generic name="faithful_rounding" value="false" />
|
||||
// Retrieval info: <generic name="gen_enable" value="true" />
|
||||
// Retrieval info: <generic name="divide_type" value="0" />
|
||||
// Retrieval info: <generic name="select_signal_enable" value="false" />
|
||||
// Retrieval info: <generic name="scale_by_pi" value="false" />
|
||||
// Retrieval info: <generic name="number_of_inputs" value="2" />
|
||||
// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
|
||||
// Retrieval info: <generic name="report_resources_to_xml" value="false" />
|
||||
// Retrieval info: <generic name="fxpt_width" value="32" />
|
||||
// Retrieval info: <generic name="fxpt_fraction" value="30" />
|
||||
// Retrieval info: <generic name="fxpt_sign" value="1" />
|
||||
// Retrieval info: <generic name="fp_out_format" value="custom" />
|
||||
// Retrieval info: <generic name="fp_out_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_out_man" value="23" />
|
||||
// Retrieval info: <generic name="fp_in_format" value="single" />
|
||||
// Retrieval info: <generic name="fp_in_exp" value="8" />
|
||||
// Retrieval info: <generic name="fp_in_man" value="23" />
|
||||
// Retrieval info: <generic name="enable_hard_fp" value="true" />
|
||||
// Retrieval info: <generic name="manual_dsp_planning" value="true" />
|
||||
// Retrieval info: <generic name="forceRegisters" value="1111" />
|
||||
// Retrieval info: <generic name="selected_device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="selected_device_speedgrade" value="7" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : fp_to_fix.vo
|
||||
// RELATED_FILES: fp_to_fix.v, dspba_library_package.vhd, dspba_library.vhd, fp_to_fix_0002.vhd
|
||||
326
system_template_de1_soc/fullfunction.v
Normal file
326
system_template_de1_soc/fullfunction.v
Normal file
|
|
@ -0,0 +1,326 @@
|
|||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
// CREATED "Tue Mar 22 14:21:41 2022"
|
||||
|
||||
module fullfunction(
|
||||
clk,
|
||||
reset,
|
||||
en,
|
||||
start,
|
||||
dataa,
|
||||
done,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire reset;
|
||||
input wire en;
|
||||
input wire start;
|
||||
input wire [31:0] dataa;
|
||||
output reg done;
|
||||
output wire [31:0] result;
|
||||
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
reg DFF_00_inst0;
|
||||
reg DFF_00_inst2;
|
||||
wire [31:0] SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
reg DFF_00_inst11;
|
||||
reg DFF_00_inst12;
|
||||
reg DFF_00_inst13;
|
||||
reg DFF_00_inst14;
|
||||
reg DFF_00_inst15;
|
||||
reg DFF_00_inst16;
|
||||
reg DFF_00_inst1;
|
||||
wire [31:0] SYNTHESIZED_WIRE_22;
|
||||
wire [31:0] SYNTHESIZED_WIRE_23;
|
||||
wire [31:0] SYNTHESIZED_WIRE_24;
|
||||
wire [31:0] SYNTHESIZED_WIRE_25;
|
||||
wire [31:0] SYNTHESIZED_WIRE_26;
|
||||
wire [31:0] SYNTHESIZED_WIRE_27;
|
||||
wire [31:0] SYNTHESIZED_WIRE_28;
|
||||
wire [31:0] SYNTHESIZED_WIRE_29;
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = 1;
|
||||
assign SYNTHESIZED_WIRE_31 = 1;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst0 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst0 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst0 <= start;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst1 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst1 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst1 <= DFF_00_inst0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
cordic b2v_00_inst10(
|
||||
.clk(clk),
|
||||
.clk_en(en),
|
||||
.start(DFF_00_inst2),
|
||||
.reset(reset),
|
||||
.dataa(SYNTHESIZED_WIRE_4),
|
||||
.done(SYNTHESIZED_WIRE_6),
|
||||
.result(SYNTHESIZED_WIRE_28));
|
||||
defparam b2v_00_inst10.stages = 16;
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst11 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst11 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst11 <= SYNTHESIZED_WIRE_6;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst12 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst12 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst12 <= DFF_00_inst11;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst13 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst13 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst13 <= DFF_00_inst12;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst14 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst14 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst14 <= DFF_00_inst13;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst15 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst15 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst15 <= DFF_00_inst14;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst16 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst16 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst16 <= DFF_00_inst15;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
done <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
done <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
done <= DFF_00_inst16;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst2 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst2 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst2 <= DFF_00_inst1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
fp_mul b2v_00_inst4(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(dataa),
|
||||
.b(dataa),
|
||||
.q(SYNTHESIZED_WIRE_24));
|
||||
|
||||
|
||||
fp_div128 b2v_00_inst5(
|
||||
.dataa(SYNTHESIZED_WIRE_22),
|
||||
.result(SYNTHESIZED_WIRE_29));
|
||||
|
||||
|
||||
fp_div2 b2v_00_inst6(
|
||||
.dataa(dataa),
|
||||
.result(SYNTHESIZED_WIRE_27));
|
||||
|
||||
|
||||
fp_sub b2v_00_inst7(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(dataa),
|
||||
.b(SYNTHESIZED_WIRE_23),
|
||||
.q(SYNTHESIZED_WIRE_22));
|
||||
|
||||
|
||||
fp_mul b2v_00_inst8(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_24),
|
||||
.b(SYNTHESIZED_WIRE_25),
|
||||
.q(SYNTHESIZED_WIRE_26));
|
||||
|
||||
|
||||
fp_add b2v_00_inst9(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_26),
|
||||
.b(SYNTHESIZED_WIRE_27),
|
||||
.q(result));
|
||||
|
||||
|
||||
fix_to_fp b2v_inst(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_28),
|
||||
.q(SYNTHESIZED_WIRE_25));
|
||||
|
||||
|
||||
fp_to_fix b2v_inst1(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_29),
|
||||
.q(SYNTHESIZED_WIRE_4));
|
||||
|
||||
|
||||
|
||||
const128 b2v_inst3(
|
||||
.result(SYNTHESIZED_WIRE_23));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
325
system_template_de1_soc/fullfunction_t.v
Normal file
325
system_template_de1_soc/fullfunction_t.v
Normal file
|
|
@ -0,0 +1,325 @@
|
|||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
// CREATED "Sun Mar 27 14:50:26 2022"
|
||||
|
||||
module fullfunction_t(
|
||||
clk,
|
||||
reset,
|
||||
en,
|
||||
start,
|
||||
dataa,
|
||||
done,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire reset;
|
||||
input wire en;
|
||||
input wire start;
|
||||
input wire [31:0] dataa;
|
||||
output reg done;
|
||||
output wire [31:0] result;
|
||||
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
reg DFF_00_inst0;
|
||||
wire [31:0] SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
reg DFF_00_inst17;
|
||||
reg DFF_00_inst11;
|
||||
reg DFF_00_inst12;
|
||||
reg DFF_00_inst13;
|
||||
reg DFF_00_inst14;
|
||||
reg DFF_00_inst15;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
reg DFF_00_inst2;
|
||||
reg DFF_00_inst1;
|
||||
wire [31:0] SYNTHESIZED_WIRE_21;
|
||||
wire [31:0] SYNTHESIZED_WIRE_22;
|
||||
wire [31:0] SYNTHESIZED_WIRE_23;
|
||||
wire [31:0] SYNTHESIZED_WIRE_24;
|
||||
wire [31:0] SYNTHESIZED_WIRE_25;
|
||||
wire [31:0] SYNTHESIZED_WIRE_26;
|
||||
wire [31:0] SYNTHESIZED_WIRE_27;
|
||||
wire [31:0] SYNTHESIZED_WIRE_28;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = 1;
|
||||
assign SYNTHESIZED_WIRE_30 = 1;
|
||||
assign SYNTHESIZED_WIRE_31 = 1;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFF_00_inst0 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFF_00_inst0 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst0 <= start;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFF_00_inst1 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFF_00_inst1 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst1 <= DFF_00_inst0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
cordic_t b2v_00_inst10(
|
||||
.clk(clk),
|
||||
.clk_en(en),
|
||||
.reset(reset),
|
||||
.dataa(SYNTHESIZED_WIRE_4),
|
||||
.result(SYNTHESIZED_WIRE_27));
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst11 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst11 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst11 <= DFF_00_inst17;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst12 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst12 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst12 <= DFF_00_inst11;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst13 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst13 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst13 <= DFF_00_inst12;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst14 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst14 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst14 <= DFF_00_inst13;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst15 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
DFF_00_inst15 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst15 <= DFF_00_inst14;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
done <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_30)
|
||||
begin
|
||||
done <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
done <= DFF_00_inst15;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst17 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_31)
|
||||
begin
|
||||
DFF_00_inst17 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst17 <= DFF_00_inst2;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFF_00_inst2 <= 0;
|
||||
end
|
||||
else
|
||||
if (!SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFF_00_inst2 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_00_inst2 <= DFF_00_inst1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
fp_mul b2v_00_inst4(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(dataa),
|
||||
.b(dataa),
|
||||
.q(SYNTHESIZED_WIRE_23));
|
||||
|
||||
|
||||
fp_div128 b2v_00_inst5(
|
||||
.dataa(SYNTHESIZED_WIRE_21),
|
||||
.result(SYNTHESIZED_WIRE_28));
|
||||
|
||||
|
||||
fp_div2 b2v_00_inst6(
|
||||
.dataa(dataa),
|
||||
.result(SYNTHESIZED_WIRE_26));
|
||||
|
||||
|
||||
fp_sub b2v_00_inst7(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(dataa),
|
||||
.b(SYNTHESIZED_WIRE_22),
|
||||
.q(SYNTHESIZED_WIRE_21));
|
||||
|
||||
|
||||
fp_mul b2v_00_inst8(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_23),
|
||||
.b(SYNTHESIZED_WIRE_24),
|
||||
.q(SYNTHESIZED_WIRE_25));
|
||||
|
||||
|
||||
fp_add b2v_00_inst9(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_25),
|
||||
.b(SYNTHESIZED_WIRE_26),
|
||||
.q(result));
|
||||
|
||||
|
||||
fix_to_fp b2v_inst(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_27),
|
||||
.q(SYNTHESIZED_WIRE_24));
|
||||
|
||||
|
||||
fp_to_fix b2v_inst1(
|
||||
.clk(clk),
|
||||
.areset(reset),
|
||||
.en(en),
|
||||
.a(SYNTHESIZED_WIRE_28),
|
||||
.q(SYNTHESIZED_WIRE_4));
|
||||
|
||||
|
||||
|
||||
const128 b2v_inst4(
|
||||
.result(SYNTHESIZED_WIRE_22));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
28
system_template_de1_soc/lpm_constant_0.v
Normal file
28
system_template_de1_soc/lpm_constant_0.v
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
// CREATED "Tue Mar 22 13:32:16 2022"
|
||||
|
||||
|
||||
module lpm_constant_0(result);
|
||||
output [31:0] result;
|
||||
|
||||
lpm_constant lpm_instance(.result(result));
|
||||
defparam lpm_instance.LPM_CVALUE = 32'b01000011000000000000000000000000;
|
||||
defparam lpm_instance.LPM_WIDTH = 32;
|
||||
|
||||
endmodule
|
||||
28
system_template_de1_soc/lpm_constant_1.v
Normal file
28
system_template_de1_soc/lpm_constant_1.v
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
// CREATED "Tue Mar 22 12:03:47 2022"
|
||||
|
||||
|
||||
module lpm_constant_1(result);
|
||||
output [31:0] result;
|
||||
|
||||
lpm_constant lpm_instance(.result(result));
|
||||
defparam lpm_instance.LPM_CVALUE = 32'b00000000000000000000000000000000;
|
||||
defparam lpm_instance.LPM_WIDTH = 32;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
// megafunction wizard: %PLL Intel FPGA IP v20.1%
|
||||
// megafunction wizard: %PLL Intel FPGA IP v21.1%
|
||||
// GENERATION: XML
|
||||
// pll.v
|
||||
|
||||
// Generated using ACDS version 20.1 711
|
||||
// Generated using ACDS version 21.1 842
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll (
|
||||
|
|
@ -47,12 +47,12 @@ endmodule
|
|||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="20.1" >
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="21.1" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
|
||||
// Retrieval info: <generic name="device" value="Unknown" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
|
|
|
|||
Loading…
Reference in a new issue