diff --git a/system_template_de1_soc/Cordic_Impl1.v b/system_template_de1_soc/Cordic_Impl1.v
new file mode 100644
index 0000000..97eb5c6
--- /dev/null
+++ b/system_template_de1_soc/Cordic_Impl1.v
@@ -0,0 +1,112 @@
+module Cordic_Impl1(
+    input clk,
+    input clk_en,
+    input start,
+    input reset,
+    input [31:0] dataa,
+    output [31:0] result,
+	 output [31:0] z_debug,
+	 output [31:0] angle_debug,
+	 output [4:0] iter_debug,
+    output done,
+	 output [31:0] y_debug
+);
+    reg [31:0] x_out,y_out,z_out;
+    reg [31:0] x_next,y_next,z_next;
+    reg [4:0] iter,iter_next;
+	 wire [31:0] angle_lut [31:0];
+    reg working, working_next;
+	 assign z_debug = z_out;
+    assign result = x_out;
+	 assign angle_debug = angle_lut[iter];
+	 assign y_debug = y_out;
+	 assign iter_debug = iter;
+    assign done = (iter==5'b11111);
+    always@(posedge clk or posedge reset) begin
+        if(reset) begin
+            x_out <= 0; 
+
+            y_out <= 0;
+
+            z_out <= 0;
+
+            iter <= 0;
+
+            working <= 0;
+
+        end else begin
+            x_out <= x_next;
+            y_out <= y_next;
+            z_out <= z_next;
+				if(done) begin
+					working <= 0;
+				end else begin
+					working <= working_next;
+				end
+            iter <= iter_next;
+        end
+    end
+
+    always @(*) begin
+        if(working) begin
+            if(~z_out[31]) begin
+                x_next <= x_out - ({{32{y_out[31]}}, y_out} >> iter);
+                y_next <= y_out + ({{32{x_out[31]}}, x_out} >> iter);
+                z_next <= z_out - angle_lut[iter];
+            end
+            else begin
+                x_next <= x_out + ({{32{y_out[31]}}, y_out} >> iter);
+                y_next <= y_out - ({{32{x_out[31]}}, x_out} >> iter);
+                z_next <= z_out + angle_lut[iter];
+            end
+            iter_next <= iter+1;
+			end 
+			else if(start) begin
+            x_next <= 32'b00100110110111010011101101101010; //Gain factor
+            y_next <= 0;
+            z_next <= dataa;
+            working_next <= 1;
+				iter_next <= 0;
+			end else begin
+				x_next <= 0; 
+            y_next <= 0;
+            z_next <= 0;
+            working_next <= 0;
+				iter_next <= 0;
+			end
+    end
+	 assign angle_lut[0] = 32'b00110010010000111111011010101000;
+     assign angle_lut[1] = 32'b00011101101011000110011100000101;
+     assign angle_lut[2] = 32'b00001111101011011011101011111100;
+     assign angle_lut[3] = 32'b00000111111101010110111010100110;
+     assign angle_lut[4] = 32'b00000011111111101010101101110110;
+     assign angle_lut[5] = 32'b00000001111111111101010101011011;
+     assign angle_lut[6] = 32'b00000000111111111111101010101010;
+     assign angle_lut[7] = 32'b00000000011111111111111101010101;
+     assign angle_lut[8] = 32'b00000000001111111111111111101010;
+     assign angle_lut[9] = 32'b00000000000111111111111111111101;
+     assign angle_lut[10] = 32'b00000000000011111111111111111111;
+     assign angle_lut[11] = 32'b00000000000001111111111111111111;
+     assign angle_lut[12] = 32'b00000000000000111111111111111111;
+     assign angle_lut[13] = 32'b00000000000000011111111111111111;
+     assign angle_lut[14] = 32'b00000000000000001111111111111111;
+     assign angle_lut[15] = 32'b00000000000000000111111111111111;
+     assign angle_lut[16] = 32'b00000000000000000011111111111111;
+     assign angle_lut[17] = 32'b00000000000000000010000000000000;
+     assign angle_lut[18] = 32'b00000000000000000000111111111111;
+     assign angle_lut[19] = 32'b00000000000000000000100000000000;
+     assign angle_lut[20] = 32'b00000000000000000000001111111111;
+     assign angle_lut[21] = 32'b00000000000000000000000111111111;
+     assign angle_lut[22] = 32'b00000000000000000000000100000000;
+     assign angle_lut[23] = 32'b00000000000000000000000001111111;
+     assign angle_lut[24] = 32'b00000000000000000000000001000000;
+     assign angle_lut[25] = 32'b00000000000000000000000000011111;
+     assign angle_lut[26] = 32'b00000000000000000000000000001111;
+     assign angle_lut[27] = 32'b00000000000000000000000000001000;
+     assign angle_lut[28] = 32'b00000000000000000000000000000011;
+     assign angle_lut[29] = 32'b00000000000000000000000000000010;
+     assign angle_lut[30] = 32'b00000000000000000000000000000000;
+     assign angle_lut[31] = 32'b00000000000000000000000000000000;
+
+	 
+endmodule
\ No newline at end of file
diff --git a/system_template_de1_soc/const128.v b/system_template_de1_soc/const128.v
new file mode 100644
index 0000000..4e90388
--- /dev/null
+++ b/system_template_de1_soc/const128.v
@@ -0,0 +1,5 @@
+module const128 (
+output [31:0] result
+);
+assign result = 32'b01000011000000000000000000000000;
+endmodule
\ No newline at end of file
diff --git a/system_template_de1_soc/cordic.v b/system_template_de1_soc/cordic.v
new file mode 100644
index 0000000..8bd2f70
--- /dev/null
+++ b/system_template_de1_soc/cordic.v
@@ -0,0 +1,110 @@
+module cordic(
+    input clk,
+    input clk_en,
+    input start,
+    input reset,
+    input [31:0] dataa,
+    output [31:0] result,
+    output done
+
+);
+    parameter [4:0] stages = 16;
+    reg [31:0] x_out,y_out,z_out;
+    reg [31:0] x_next,y_next,z_next;
+    reg [4:0] iter,iter_next;
+	 wire [31:0] angle_lut [31:0];
+    reg working, working_next;
+	 assign z_debug = z_out;
+    assign result = x_out;
+	 assign angle_debug = angle_lut[iter];
+	 assign y_debug = y_out;
+	 assign iter_debug = iter;
+    assign done = (iter==stages);
+    always@(posedge clk or posedge reset) begin
+        if(reset) begin
+            x_out <= 0; 
+
+            y_out <= 0;
+
+            z_out <= 0;
+
+            iter <= 0;
+
+            working <= 0;
+
+        end else begin
+            x_out <= x_next;
+            y_out <= y_next;
+            z_out <= z_next;
+				if(done) begin
+					working <= 0;
+				end else begin
+					working <= working_next;
+				end
+            iter <= iter_next;
+        end
+    end
+
+    always @(*) begin
+        if(working) begin
+            if(~z_out[31]) begin
+                x_next <= x_out - ({{32{y_out[31]}}, y_out} >> iter);
+                y_next <= y_out + ({{32{x_out[31]}}, x_out} >> iter);
+                z_next <= z_out - angle_lut[iter];
+            end
+            else begin
+                x_next <= x_out + ({{32{y_out[31]}}, y_out} >> iter);
+                y_next <= y_out - ({{32{x_out[31]}}, x_out} >> iter);
+                z_next <= z_out + angle_lut[iter];
+            end
+            iter_next <= iter+1;
+			end 
+			else if(start) begin
+            x_next <= 32'b00100110110111010011101101101010; //Gain factor
+            y_next <= 0;
+            z_next <= dataa;
+            working_next <= 1;
+				iter_next <= 0;
+			end else begin
+				x_next <= 0; 
+            y_next <= 0;
+            z_next <= 0;
+            working_next <= 0;
+				iter_next <= 0;
+			end
+    end
+	 assign angle_lut[0] = 32'b00110010010000111111011010101001;
+     assign angle_lut[1] = 32'b00011101101011000110011100000101;
+     assign angle_lut[2] = 32'b00001111101011011011101011111101;
+     assign angle_lut[3] = 32'b00000111111101010110111010100111;
+     assign angle_lut[4] = 32'b00000011111111101010101101110111;
+     assign angle_lut[5] = 32'b00000001111111111101010101011100;
+     assign angle_lut[6] = 32'b00000000111111111111101010101011;
+     assign angle_lut[7] = 32'b00000000011111111111111101010101;
+     assign angle_lut[8] = 32'b00000000001111111111111111101011;
+     assign angle_lut[9] = 32'b00000000000111111111111111111101;
+     assign angle_lut[10] = 32'b00000000000100000000000000000000;
+     assign angle_lut[11] = 32'b00000000000010000000000000000000;
+     assign angle_lut[12] = 32'b00000000000001000000000000000000;
+     assign angle_lut[13] = 32'b00000000000000100000000000000000;
+     assign angle_lut[14] = 32'b00000000000000010000000000000000;
+     assign angle_lut[15] = 32'b00000000000000001000000000000000;
+     assign angle_lut[16] = 32'b00000000000000000100000000000000;
+     assign angle_lut[17] = 32'b00000000000000000010000000000000;
+     assign angle_lut[18] = 32'b00000000000000000001000000000000;
+     assign angle_lut[19] = 32'b00000000000000000000100000000000;
+     assign angle_lut[20] = 32'b00000000000000000000010000000000;
+     assign angle_lut[21] = 32'b00000000000000000000001000000000;
+     assign angle_lut[22] = 32'b00000000000000000000000100000000;
+     assign angle_lut[23] = 32'b00000000000000000000000010000000;
+     assign angle_lut[24] = 32'b00000000000000000000000001000000;
+     assign angle_lut[25] = 32'b00000000000000000000000000100000;
+     assign angle_lut[26] = 32'b00000000000000000000000000010000;
+     assign angle_lut[27] = 32'b00000000000000000000000000001000;
+     assign angle_lut[28] = 32'b00000000000000000000000000000100;
+     assign angle_lut[29] = 32'b00000000000000000000000000000010;
+     assign angle_lut[30] = 32'b00000000000000000000000000000001;
+     assign angle_lut[31] = 32'b00000000000000000000000000000001;
+
+	 
+endmodule
\ No newline at end of file
diff --git a/system_template_de1_soc/cordic_t.v b/system_template_de1_soc/cordic_t.v
new file mode 100644
index 0000000..79f1724
--- /dev/null
+++ b/system_template_de1_soc/cordic_t.v
@@ -0,0 +1,73 @@
+module cordic_t(
+	input clk,
+	input clk_en,
+	input reset,
+	input [31:0] dataa,
+	output [31:0] result
+);
+	reg [31:0] x[16:0];
+	reg [31:0] y[16:0];
+	reg [31:0] z[16:0];
+	integer i;
+	wire [31:0] angle_lut [31:0];
+	assign result = x[16];
+
+	always @(*) begin
+		 if(reset) begin
+			for(i = 0 ;i < 17; i = i+1) begin
+				x[i] <= 0;
+				y[i] <= 0;
+				z[i] <= 0;
+			end
+		end else begin
+			x[0] <= 32'b00100110110111010011101101101010;
+			y[0] <= 0;
+			z[0] <= dataa;
+			for(i = 0 ;i < 16; i = i+1) begin
+				if(~z[i][31]) begin
+					x[i+1] <= x[i] - ({{32{y[i][31]}}, y[i]} >> i);
+					y[i+1] <= y[i] + ({{32{x[i][31]}}, x[i]} >> i);
+					z[i+1] <= z[i] - angle_lut[i];
+				end
+				else begin
+					x[i+1] <= x[i] + ({{32{y[i][31]}}, y[i]} >> i);
+					y[i+1] <= y[i] - ({{32{x[i][31]}}, x[i]} >> i);
+					z[i+1] <= z[i] + angle_lut[i];
+				end
+			end
+		end		
+	end
+
+	assign angle_lut[0] = 32'b00110010010000111111011010101001;
+	assign angle_lut[1] = 32'b00011101101011000110011100000101;
+	assign angle_lut[2] = 32'b00001111101011011011101011111101;
+	assign angle_lut[3] = 32'b00000111111101010110111010100111;
+	assign angle_lut[4] = 32'b00000011111111101010101101110111;
+	assign angle_lut[5] = 32'b00000001111111111101010101011100;
+	assign angle_lut[6] = 32'b00000000111111111111101010101011;
+	assign angle_lut[7] = 32'b00000000011111111111111101010101;
+	assign angle_lut[8] = 32'b00000000001111111111111111101011;
+	assign angle_lut[9] = 32'b00000000000111111111111111111101;
+	assign angle_lut[10] = 32'b00000000000100000000000000000000;
+	assign angle_lut[11] = 32'b00000000000010000000000000000000;
+	assign angle_lut[12] = 32'b00000000000001000000000000000000;
+	assign angle_lut[13] = 32'b00000000000000100000000000000000;
+	assign angle_lut[14] = 32'b00000000000000010000000000000000;
+	assign angle_lut[15] = 32'b00000000000000001000000000000000;
+	assign angle_lut[16] = 32'b00000000000000000100000000000000;
+	assign angle_lut[17] = 32'b00000000000000000010000000000000;
+	assign angle_lut[18] = 32'b00000000000000000001000000000000;
+	assign angle_lut[19] = 32'b00000000000000000000100000000000;
+	assign angle_lut[20] = 32'b00000000000000000000010000000000;
+	assign angle_lut[21] = 32'b00000000000000000000001000000000;
+	assign angle_lut[22] = 32'b00000000000000000000000100000000;
+	assign angle_lut[23] = 32'b00000000000000000000000010000000;
+	assign angle_lut[24] = 32'b00000000000000000000000001000000;
+	assign angle_lut[25] = 32'b00000000000000000000000000100000;
+	assign angle_lut[26] = 32'b00000000000000000000000000010000;
+	assign angle_lut[27] = 32'b00000000000000000000000000001000;
+	assign angle_lut[28] = 32'b00000000000000000000000000000100;
+	assign angle_lut[29] = 32'b00000000000000000000000000000010;
+	assign angle_lut[30] = 32'b00000000000000000000000000000001;
+	assign angle_lut[31] = 32'b00000000000000000000000000000001;
+endmodule
\ No newline at end of file
diff --git a/system_template_de1_soc/dualfunction.v b/system_template_de1_soc/dualfunction.v
new file mode 100644
index 0000000..31a53f3
--- /dev/null
+++ b/system_template_de1_soc/dualfunction.v
@@ -0,0 +1,122 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// PROGRAM		"Quartus Prime"
+// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+// CREATED		"Tue Mar 22 14:47:05 2022"
+
+module dualfunction(
+	clk,
+	reset,
+	en,
+	start,
+	dataa,
+	datab,
+	done,
+	result
+);
+
+
+input wire	clk;
+input wire	reset;
+input wire	en;
+input wire	start;
+input wire	[31:0] dataa;
+input wire	[31:0] datab;
+output reg	done;
+output wire	[31:0] result;
+
+wire	[31:0] SYNTHESIZED_WIRE_0;
+wire	[31:0] SYNTHESIZED_WIRE_1;
+wire	SYNTHESIZED_WIRE_2;
+wire	SYNTHESIZED_WIRE_3;
+wire	SYNTHESIZED_WIRE_9;
+wire	SYNTHESIZED_WIRE_5;
+reg	DFF_inst4;
+
+assign	SYNTHESIZED_WIRE_9 = 1;
+
+
+
+
+fullfunction	b2v_inst(
+	.clk(clk),
+	.reset(reset),
+	.en(en),
+	.start(start),
+	.dataa(dataa),
+	.done(SYNTHESIZED_WIRE_2),
+	.result(SYNTHESIZED_WIRE_0));
+
+
+fullfunction	b2v_inst1(
+	.clk(clk),
+	.reset(reset),
+	.en(en),
+	.start(start),
+	.dataa(datab),
+	.done(SYNTHESIZED_WIRE_3),
+	.result(SYNTHESIZED_WIRE_1));
+
+
+fp_add	b2v_inst2(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_0),
+	.b(SYNTHESIZED_WIRE_1),
+	.q(result));
+
+assign	SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_3;
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
+begin
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	DFF_inst4 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	DFF_inst4 <= 1;
+	end
+else
+	begin
+	DFF_inst4 <= SYNTHESIZED_WIRE_5;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
+begin
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	done <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	done <= 1;
+	end
+else
+	begin
+	done <= DFF_inst4;
+	end
+end
+
+
+
+endmodule
diff --git a/system_template_de1_soc/dualfunction_t.v b/system_template_de1_soc/dualfunction_t.v
new file mode 100644
index 0000000..5708ac2
--- /dev/null
+++ b/system_template_de1_soc/dualfunction_t.v
@@ -0,0 +1,122 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// PROGRAM		"Quartus Prime"
+// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+// CREATED		"Sun Mar 27 15:17:39 2022"
+
+module dualfunction_t(
+	clk,
+	reset,
+	en,
+	start,
+	dataa,
+	datab,
+	done,
+	result
+);
+
+
+input wire	clk;
+input wire	reset;
+input wire	en;
+input wire	start;
+input wire	[31:0] dataa;
+input wire	[31:0] datab;
+output reg	done;
+output wire	[31:0] result;
+
+wire	[31:0] SYNTHESIZED_WIRE_0;
+wire	[31:0] SYNTHESIZED_WIRE_1;
+wire	SYNTHESIZED_WIRE_2;
+wire	SYNTHESIZED_WIRE_3;
+wire	SYNTHESIZED_WIRE_9;
+wire	SYNTHESIZED_WIRE_5;
+reg	DFF_inst4;
+
+assign	SYNTHESIZED_WIRE_9 = 1;
+
+
+
+
+fullfunction_t	b2v_inst(
+	.clk(clk),
+	.reset(reset),
+	.en(en),
+	.start(start),
+	.dataa(dataa),
+	.done(SYNTHESIZED_WIRE_2),
+	.result(SYNTHESIZED_WIRE_0));
+
+
+fullfunction_t	b2v_inst1(
+	.clk(clk),
+	.reset(reset),
+	.en(en),
+	.start(start),
+	.dataa(datab),
+	.done(SYNTHESIZED_WIRE_3),
+	.result(SYNTHESIZED_WIRE_1));
+
+
+fp_add	b2v_inst2(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_0),
+	.b(SYNTHESIZED_WIRE_1),
+	.q(result));
+
+assign	SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_3;
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
+begin
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	DFF_inst4 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	DFF_inst4 <= 1;
+	end
+else
+	begin
+	DFF_inst4 <= SYNTHESIZED_WIRE_5;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
+begin
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	done <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_9)
+	begin
+	done <= 1;
+	end
+else
+	begin
+	done <= DFF_inst4;
+	end
+end
+
+
+
+endmodule
diff --git a/system_template_de1_soc/first_nios2_system.qsys b/system_template_de1_soc/first_nios2_system.qsys
index 17c9748..3188fa9 100644
--- a/system_template_de1_soc/first_nios2_system.qsys
+++ b/system_template_de1_soc/first_nios2_system.qsys
@@ -21,7 +21,7 @@
    {
       datum _sortIndex
       {
-         value = "2";
+         value = "1";
          type = "int";
       }
    }
@@ -33,11 +33,107 @@
          type = "String";
       }
    }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element first_nios2_system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element fp_add
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element fp_mul
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element fp_sub
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
    element jtag_uart
    {
       datum _sortIndex
       {
-         value = "3";
+         value = "2";
          type = "int";
       }
    }
@@ -53,7 +149,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "5";
          type = "int";
       }
    }
@@ -65,27 +161,11 @@
          type = "String";
       }
    }
-   element onchip_mem
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element onchip_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
    element sdram
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "6";
          type = "int";
       }
    }
@@ -101,7 +181,7 @@
    {
       datum _sortIndex
       {
-         value = "4";
+         value = "3";
          type = "int";
       }
    }
@@ -117,7 +197,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "4";
          type = "int";
       }
    }
@@ -177,7 +257,7 @@
   <parameter name="cpuArchRev" value="1" />
   <parameter name="cpuID" value="0" />
   <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo"><![CDATA[<info><slave name="fp_add" baseAddress="0" addressSpan="1" clockCycleType="MULTICYCLE" /><slave name="fp_sub" baseAddress="1" addressSpan="1" clockCycleType="MULTICYCLE" /><slave name="fp_mul" baseAddress="2" addressSpan="1" clockCycleType="MULTICYCLE" /></info>]]></parameter>
   <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
   <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
   <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
@@ -251,8 +331,8 @@
   <parameter name="mpu_numOfInstRegion" value="8" />
   <parameter name="mpu_useLimit" value="false" />
   <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="2" />
-  <parameter name="mul_64_impl" value="1" />
+  <parameter name="mul_32_impl" value="0" />
+  <parameter name="mul_64_impl" value="0" />
   <parameter name="mul_shift_choice" value="1" />
   <parameter name="ocimem_ramBlockType" value="Automatic" />
   <parameter name="ocimem_ramInit" value="false" />
@@ -342,6 +422,9 @@
   <parameter name="tracefilename" value="" />
   <parameter name="userDefinedSettings" value="" />
  </module>
+ <module name="fp_add" kind="fp_add" version="20.1" enabled="1" />
+ <module name="fp_mul" kind="fp_mul" version="20.1" enabled="1" />
+ <module name="fp_sub" kind="fp_sub" version="20.1" enabled="1" />
  <module
    name="jtag_uart"
    kind="altera_avalon_jtag_uart"
@@ -375,38 +458,6 @@
   <parameter name="simDrivenValue" value="0" />
   <parameter name="width" value="8" />
  </module>
- <module
-   name="onchip_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="20.1"
-   enabled="0">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">first_nios2_system_onchip_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="dataWidth2" value="32" />
-  <parameter name="deviceFamily" value="Cyclone V" />
-  <parameter name="deviceFeatures">COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 1 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="enPRInitMode" value="false" />
-  <parameter name="enableDiffWidth" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="65536" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
  <module
    name="sdram"
    kind="altera_avalon_new_sdram_controller"
@@ -444,8 +495,8 @@
   <parameter name="alwaysRun" value="false" />
   <parameter name="counterSize" value="32" />
   <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="period" value="100" />
+  <parameter name="periodUnits" value="USEC" />
   <parameter name="resetOutput" value="false" />
   <parameter name="snapshot" value="true" />
   <parameter name="systemFrequency" value="50000000" />
@@ -457,7 +508,7 @@
    kind="altera_avalon_sysid_qsys"
    version="20.1"
    enabled="1">
-  <parameter name="id" value="0" />
+  <parameter name="id" value="305419896" />
  </module>
  <connection
    kind="avalon"
@@ -486,15 +537,6 @@
   <parameter name="baseAddress" value="0x01000800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="cpu.data_master"
-   end="onchip_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="avalon"
    version="20.1"
@@ -523,15 +565,6 @@
   <parameter name="baseAddress" value="0x01000800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="cpu.instruction_master"
-   end="onchip_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="avalon"
    version="20.1"
@@ -547,7 +580,6 @@
  <connection kind="clock" version="20.1" start="clk_0.clk" end="sysid.clk" />
  <connection kind="clock" version="20.1" start="clk_0.clk" end="led_pio.clk" />
  <connection kind="clock" version="20.1" start="clk_0.clk" end="sdram.clk" />
- <connection kind="clock" version="20.1" start="clk_0.clk" end="onchip_mem.clk1" />
  <connection
    kind="interrupt"
    version="20.1"
@@ -558,6 +590,33 @@
  <connection kind="interrupt" version="20.1" start="cpu.irq" end="jtag_uart.irq">
   <parameter name="irqNumber" value="16" />
  </connection>
+ <connection
+   kind="nios_custom_instruction"
+   version="20.1"
+   start="cpu.custom_instruction_master"
+   end="fp_add.fp_add_slave">
+  <parameter name="CIName" value="fp_add" />
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0" />
+ </connection>
+ <connection
+   kind="nios_custom_instruction"
+   version="20.1"
+   start="cpu.custom_instruction_master"
+   end="fp_mul.fp_mul_slave">
+  <parameter name="CIName" value="fp_mul" />
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="2" />
+ </connection>
+ <connection
+   kind="nios_custom_instruction"
+   version="20.1"
+   start="cpu.custom_instruction_master"
+   end="fp_sub.fp_sub_slave">
+  <parameter name="CIName" value="fp_sub" />
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="1" />
+ </connection>
  <connection kind="reset" version="20.1" start="clk_0.clk_reset" end="cpu.reset" />
  <connection
    kind="reset"
@@ -576,11 +635,6 @@
    start="clk_0.clk_reset"
    end="led_pio.reset" />
  <connection kind="reset" version="20.1" start="clk_0.clk_reset" end="sdram.reset" />
- <connection
-   kind="reset"
-   version="20.1"
-   start="clk_0.clk_reset"
-   end="onchip_mem.reset1" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
  <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/system_template_de1_soc/fix_to_fp.v b/system_template_de1_soc/fix_to_fp.v
new file mode 100644
index 0000000..73c079e
--- /dev/null
+++ b/system_template_de1_soc/fix_to_fp.v
@@ -0,0 +1,92 @@
+// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
+// GENERATION: XML
+// fix_to_fp.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module fix_to_fp (
+		input  wire        clk,    //    clk.clk
+		input  wire        areset, // areset.reset
+		input  wire [0:0]  en,     //     en.en
+		input  wire [31:0] a,      //      a.a
+		output wire [31:0] q       //      q.q
+	);
+
+	fix_to_fp_0002 fix_to_fp_inst (
+		.clk    (clk),    //    clk.clk
+		.areset (areset), // areset.reset
+		.en     (en),     //     en.en
+		.a      (a),      //      a.a
+		.q      (q)       //      q.q
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2022 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
+// Retrieval info: 	<generic name="FUNCTION_FAMILY" value="CONVERT" />
+// Retrieval info: 	<generic name="ARITH_function" value="ADD" />
+// Retrieval info: 	<generic name="CONVERT_function" value="FXP_FP" />
+// Retrieval info: 	<generic name="ALL_function" value="ADD" />
+// Retrieval info: 	<generic name="EXP_LOG_function" value="EXPE" />
+// Retrieval info: 	<generic name="TRIG_function" value="SIN" />
+// Retrieval info: 	<generic name="COMPARE_function" value="MIN" />
+// Retrieval info: 	<generic name="ROOTS_function" value="SQRT" />
+// Retrieval info: 	<generic name="fp_format" value="single" />
+// Retrieval info: 	<generic name="fp_exp" value="8" />
+// Retrieval info: 	<generic name="fp_man" value="23" />
+// Retrieval info: 	<generic name="exponent_width" value="23" />
+// Retrieval info: 	<generic name="frequency_target" value="50" />
+// Retrieval info: 	<generic name="latency_target" value="2" />
+// Retrieval info: 	<generic name="performance_goal" value="combined" />
+// Retrieval info: 	<generic name="rounding_mode" value="nearest with tie breaking away from zero" />
+// Retrieval info: 	<generic name="faithful_rounding" value="false" />
+// Retrieval info: 	<generic name="gen_enable" value="true" />
+// Retrieval info: 	<generic name="divide_type" value="0" />
+// Retrieval info: 	<generic name="select_signal_enable" value="false" />
+// Retrieval info: 	<generic name="scale_by_pi" value="false" />
+// Retrieval info: 	<generic name="number_of_inputs" value="2" />
+// Retrieval info: 	<generic name="trig_no_range_reduction" value="false" />
+// Retrieval info: 	<generic name="report_resources_to_xml" value="false" />
+// Retrieval info: 	<generic name="fxpt_width" value="32" />
+// Retrieval info: 	<generic name="fxpt_fraction" value="30" />
+// Retrieval info: 	<generic name="fxpt_sign" value="1" />
+// Retrieval info: 	<generic name="fp_out_format" value="single" />
+// Retrieval info: 	<generic name="fp_out_exp" value="8" />
+// Retrieval info: 	<generic name="fp_out_man" value="23" />
+// Retrieval info: 	<generic name="fp_in_format" value="single" />
+// Retrieval info: 	<generic name="fp_in_exp" value="8" />
+// Retrieval info: 	<generic name="fp_in_man" value="23" />
+// Retrieval info: 	<generic name="enable_hard_fp" value="true" />
+// Retrieval info: 	<generic name="manual_dsp_planning" value="true" />
+// Retrieval info: 	<generic name="forceRegisters" value="1111" />
+// Retrieval info: 	<generic name="selected_device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="selected_device_speedgrade" value="7" />
+// Retrieval info: </instance>
+// IPFS_FILES : fix_to_fp.vo
+// RELATED_FILES: fix_to_fp.v, dspba_library_package.vhd, dspba_library.vhd, fix_to_fp_0002.vhd
diff --git a/system_template_de1_soc/fp_div128.v b/system_template_de1_soc/fp_div128.v
new file mode 100644
index 0000000..6cbc26e
--- /dev/null
+++ b/system_template_de1_soc/fp_div128.v
@@ -0,0 +1,8 @@
+module fp_div128 ( 
+input [31:0] dataa,
+output [31:0] result
+);
+wire [7:0] NewExp;
+assign NewExp = dataa[30:23]-7;
+assign result = (dataa[30:23]<=6) ? 0 : {dataa[31],NewExp,dataa[22:0]};
+endmodule
\ No newline at end of file
diff --git a/system_template_de1_soc/fp_div2.v b/system_template_de1_soc/fp_div2.v
new file mode 100644
index 0000000..70041eb
--- /dev/null
+++ b/system_template_de1_soc/fp_div2.v
@@ -0,0 +1,8 @@
+module fp_div2 ( 
+input [31:0] dataa,
+output [31:0] result
+);
+wire [7:0] NewExp;
+assign NewExp = dataa[30:23]-1;
+assign result = (dataa[30:23]==0) ? 0 : {dataa[31],NewExp,dataa[22:0]};
+endmodule
\ No newline at end of file
diff --git a/system_template_de1_soc/fp_sum.v b/system_template_de1_soc/fp_sum.v
new file mode 100644
index 0000000..0b41023
--- /dev/null
+++ b/system_template_de1_soc/fp_sum.v
@@ -0,0 +1,94 @@
+// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
+// GENERATION: XML
+// fp_sum.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module fp_sum (
+		input  wire        clk,    //    clk.clk
+		input  wire        areset, // areset.reset
+		input  wire [0:0]  en,     //     en.en
+		input  wire [31:0] a,      //      a.a
+		input  wire [31:0] b,      //      b.b
+		output wire [31:0] q       //      q.q
+	);
+
+	fp_sum_0002 fp_sum_inst (
+		.clk    (clk),    //    clk.clk
+		.areset (areset), // areset.reset
+		.en     (en),     //     en.en
+		.a      (a),      //      a.a
+		.b      (b),      //      b.b
+		.q      (q)       //      q.q
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2022 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
+// Retrieval info: 	<generic name="FUNCTION_FAMILY" value="ARITH" />
+// Retrieval info: 	<generic name="ARITH_function" value="ADD" />
+// Retrieval info: 	<generic name="CONVERT_function" value="FXP_FP" />
+// Retrieval info: 	<generic name="ALL_function" value="ADD" />
+// Retrieval info: 	<generic name="EXP_LOG_function" value="EXPE" />
+// Retrieval info: 	<generic name="TRIG_function" value="SIN" />
+// Retrieval info: 	<generic name="COMPARE_function" value="MIN" />
+// Retrieval info: 	<generic name="ROOTS_function" value="SQRT" />
+// Retrieval info: 	<generic name="fp_format" value="single" />
+// Retrieval info: 	<generic name="fp_exp" value="8" />
+// Retrieval info: 	<generic name="fp_man" value="23" />
+// Retrieval info: 	<generic name="exponent_width" value="23" />
+// Retrieval info: 	<generic name="frequency_target" value="50" />
+// Retrieval info: 	<generic name="latency_target" value="2" />
+// Retrieval info: 	<generic name="performance_goal" value="combined" />
+// Retrieval info: 	<generic name="rounding_mode" value="nearest with tie breaking away from zero" />
+// Retrieval info: 	<generic name="faithful_rounding" value="false" />
+// Retrieval info: 	<generic name="gen_enable" value="true" />
+// Retrieval info: 	<generic name="divide_type" value="0" />
+// Retrieval info: 	<generic name="select_signal_enable" value="false" />
+// Retrieval info: 	<generic name="scale_by_pi" value="false" />
+// Retrieval info: 	<generic name="number_of_inputs" value="2" />
+// Retrieval info: 	<generic name="trig_no_range_reduction" value="false" />
+// Retrieval info: 	<generic name="report_resources_to_xml" value="false" />
+// Retrieval info: 	<generic name="fxpt_width" value="32" />
+// Retrieval info: 	<generic name="fxpt_fraction" value="0" />
+// Retrieval info: 	<generic name="fxpt_sign" value="1" />
+// Retrieval info: 	<generic name="fp_out_format" value="single" />
+// Retrieval info: 	<generic name="fp_out_exp" value="8" />
+// Retrieval info: 	<generic name="fp_out_man" value="23" />
+// Retrieval info: 	<generic name="fp_in_format" value="single" />
+// Retrieval info: 	<generic name="fp_in_exp" value="8" />
+// Retrieval info: 	<generic name="fp_in_man" value="23" />
+// Retrieval info: 	<generic name="enable_hard_fp" value="true" />
+// Retrieval info: 	<generic name="manual_dsp_planning" value="true" />
+// Retrieval info: 	<generic name="forceRegisters" value="1111" />
+// Retrieval info: 	<generic name="selected_device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="selected_device_speedgrade" value="7" />
+// Retrieval info: </instance>
+// IPFS_FILES : fp_sum.vo
+// RELATED_FILES: fp_sum.v, dspba_library_package.vhd, dspba_library.vhd, fp_sum_0002.vhd
diff --git a/system_template_de1_soc/fp_to_fix.v b/system_template_de1_soc/fp_to_fix.v
new file mode 100644
index 0000000..c40f600
--- /dev/null
+++ b/system_template_de1_soc/fp_to_fix.v
@@ -0,0 +1,92 @@
+// megafunction wizard: %FP_FUNCTIONS Intel FPGA IP v20.1%
+// GENERATION: XML
+// fp_to_fix.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module fp_to_fix (
+		input  wire        clk,    //    clk.clk
+		input  wire        areset, // areset.reset
+		input  wire [0:0]  en,     //     en.en
+		input  wire [31:0] a,      //      a.a
+		output wire [31:0] q       //      q.q
+	);
+
+	fp_to_fix_0002 fp_to_fix_inst (
+		.clk    (clk),    //    clk.clk
+		.areset (areset), // areset.reset
+		.en     (en),     //     en.en
+		.a      (a),      //      a.a
+		.q      (q)       //      q.q
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2022 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_fp_functions" version="20.1" >
+// Retrieval info: 	<generic name="FUNCTION_FAMILY" value="CONVERT" />
+// Retrieval info: 	<generic name="ARITH_function" value="ADD" />
+// Retrieval info: 	<generic name="CONVERT_function" value="FP_FXP" />
+// Retrieval info: 	<generic name="ALL_function" value="ADD" />
+// Retrieval info: 	<generic name="EXP_LOG_function" value="EXPE" />
+// Retrieval info: 	<generic name="TRIG_function" value="SIN" />
+// Retrieval info: 	<generic name="COMPARE_function" value="MIN" />
+// Retrieval info: 	<generic name="ROOTS_function" value="SQRT" />
+// Retrieval info: 	<generic name="fp_format" value="single" />
+// Retrieval info: 	<generic name="fp_exp" value="8" />
+// Retrieval info: 	<generic name="fp_man" value="23" />
+// Retrieval info: 	<generic name="exponent_width" value="23" />
+// Retrieval info: 	<generic name="frequency_target" value="50" />
+// Retrieval info: 	<generic name="latency_target" value="1" />
+// Retrieval info: 	<generic name="performance_goal" value="combined" />
+// Retrieval info: 	<generic name="rounding_mode" value="nearest with tie breaking away from zero" />
+// Retrieval info: 	<generic name="faithful_rounding" value="false" />
+// Retrieval info: 	<generic name="gen_enable" value="true" />
+// Retrieval info: 	<generic name="divide_type" value="0" />
+// Retrieval info: 	<generic name="select_signal_enable" value="false" />
+// Retrieval info: 	<generic name="scale_by_pi" value="false" />
+// Retrieval info: 	<generic name="number_of_inputs" value="2" />
+// Retrieval info: 	<generic name="trig_no_range_reduction" value="false" />
+// Retrieval info: 	<generic name="report_resources_to_xml" value="false" />
+// Retrieval info: 	<generic name="fxpt_width" value="32" />
+// Retrieval info: 	<generic name="fxpt_fraction" value="30" />
+// Retrieval info: 	<generic name="fxpt_sign" value="1" />
+// Retrieval info: 	<generic name="fp_out_format" value="custom" />
+// Retrieval info: 	<generic name="fp_out_exp" value="8" />
+// Retrieval info: 	<generic name="fp_out_man" value="23" />
+// Retrieval info: 	<generic name="fp_in_format" value="single" />
+// Retrieval info: 	<generic name="fp_in_exp" value="8" />
+// Retrieval info: 	<generic name="fp_in_man" value="23" />
+// Retrieval info: 	<generic name="enable_hard_fp" value="true" />
+// Retrieval info: 	<generic name="manual_dsp_planning" value="true" />
+// Retrieval info: 	<generic name="forceRegisters" value="1111" />
+// Retrieval info: 	<generic name="selected_device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="selected_device_speedgrade" value="7" />
+// Retrieval info: </instance>
+// IPFS_FILES : fp_to_fix.vo
+// RELATED_FILES: fp_to_fix.v, dspba_library_package.vhd, dspba_library.vhd, fp_to_fix_0002.vhd
diff --git a/system_template_de1_soc/fullfunction.v b/system_template_de1_soc/fullfunction.v
new file mode 100644
index 0000000..4ce3cdf
--- /dev/null
+++ b/system_template_de1_soc/fullfunction.v
@@ -0,0 +1,326 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// PROGRAM		"Quartus Prime"
+// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+// CREATED		"Tue Mar 22 14:21:41 2022"
+
+module fullfunction(
+	clk,
+	reset,
+	en,
+	start,
+	dataa,
+	done,
+	result
+);
+
+
+input wire	clk;
+input wire	reset;
+input wire	en;
+input wire	start;
+input wire	[31:0] dataa;
+output reg	done;
+output wire	[31:0] result;
+
+wire	SYNTHESIZED_WIRE_30;
+reg	DFF_00_inst0;
+reg	DFF_00_inst2;
+wire	[31:0] SYNTHESIZED_WIRE_4;
+wire	SYNTHESIZED_WIRE_31;
+wire	SYNTHESIZED_WIRE_6;
+reg	DFF_00_inst11;
+reg	DFF_00_inst12;
+reg	DFF_00_inst13;
+reg	DFF_00_inst14;
+reg	DFF_00_inst15;
+reg	DFF_00_inst16;
+reg	DFF_00_inst1;
+wire	[31:0] SYNTHESIZED_WIRE_22;
+wire	[31:0] SYNTHESIZED_WIRE_23;
+wire	[31:0] SYNTHESIZED_WIRE_24;
+wire	[31:0] SYNTHESIZED_WIRE_25;
+wire	[31:0] SYNTHESIZED_WIRE_26;
+wire	[31:0] SYNTHESIZED_WIRE_27;
+wire	[31:0] SYNTHESIZED_WIRE_28;
+wire	[31:0] SYNTHESIZED_WIRE_29;
+
+assign	SYNTHESIZED_WIRE_30 = 1;
+assign	SYNTHESIZED_WIRE_31 = 1;
+
+
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst0 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst0 <= 1;
+	end
+else
+	begin
+	DFF_00_inst0 <= start;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst1 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst1 <= 1;
+	end
+else
+	begin
+	DFF_00_inst1 <= DFF_00_inst0;
+	end
+end
+
+
+cordic	b2v_00_inst10(
+	.clk(clk),
+	.clk_en(en),
+	.start(DFF_00_inst2),
+	.reset(reset),
+	.dataa(SYNTHESIZED_WIRE_4),
+	.done(SYNTHESIZED_WIRE_6),
+	.result(SYNTHESIZED_WIRE_28));
+	defparam	b2v_00_inst10.stages = 16;
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst11 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst11 <= 1;
+	end
+else
+	begin
+	DFF_00_inst11 <= SYNTHESIZED_WIRE_6;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst12 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst12 <= 1;
+	end
+else
+	begin
+	DFF_00_inst12 <= DFF_00_inst11;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst13 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst13 <= 1;
+	end
+else
+	begin
+	DFF_00_inst13 <= DFF_00_inst12;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst14 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst14 <= 1;
+	end
+else
+	begin
+	DFF_00_inst14 <= DFF_00_inst13;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst15 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst15 <= 1;
+	end
+else
+	begin
+	DFF_00_inst15 <= DFF_00_inst14;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst16 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst16 <= 1;
+	end
+else
+	begin
+	DFF_00_inst16 <= DFF_00_inst15;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	done <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	done <= 1;
+	end
+else
+	begin
+	done <= DFF_00_inst16;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst2 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst2 <= 1;
+	end
+else
+	begin
+	DFF_00_inst2 <= DFF_00_inst1;
+	end
+end
+
+
+fp_mul	b2v_00_inst4(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(dataa),
+	.b(dataa),
+	.q(SYNTHESIZED_WIRE_24));
+
+
+fp_div128	b2v_00_inst5(
+	.dataa(SYNTHESIZED_WIRE_22),
+	.result(SYNTHESIZED_WIRE_29));
+
+
+fp_div2	b2v_00_inst6(
+	.dataa(dataa),
+	.result(SYNTHESIZED_WIRE_27));
+
+
+fp_sub	b2v_00_inst7(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(dataa),
+	.b(SYNTHESIZED_WIRE_23),
+	.q(SYNTHESIZED_WIRE_22));
+
+
+fp_mul	b2v_00_inst8(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_24),
+	.b(SYNTHESIZED_WIRE_25),
+	.q(SYNTHESIZED_WIRE_26));
+
+
+fp_add	b2v_00_inst9(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_26),
+	.b(SYNTHESIZED_WIRE_27),
+	.q(result));
+
+
+fix_to_fp	b2v_inst(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_28),
+	.q(SYNTHESIZED_WIRE_25));
+
+
+fp_to_fix	b2v_inst1(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_29),
+	.q(SYNTHESIZED_WIRE_4));
+
+
+
+const128	b2v_inst3(
+	.result(SYNTHESIZED_WIRE_23));
+
+
+
+endmodule
diff --git a/system_template_de1_soc/fullfunction_t.v b/system_template_de1_soc/fullfunction_t.v
new file mode 100644
index 0000000..279feee
--- /dev/null
+++ b/system_template_de1_soc/fullfunction_t.v
@@ -0,0 +1,325 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// PROGRAM		"Quartus Prime"
+// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+// CREATED		"Sun Mar 27 14:50:26 2022"
+
+module fullfunction_t(
+	clk,
+	reset,
+	en,
+	start,
+	dataa,
+	done,
+	result
+);
+
+
+input wire	clk;
+input wire	reset;
+input wire	en;
+input wire	start;
+input wire	[31:0] dataa;
+output reg	done;
+output wire	[31:0] result;
+
+wire	SYNTHESIZED_WIRE_29;
+reg	DFF_00_inst0;
+wire	[31:0] SYNTHESIZED_WIRE_4;
+wire	SYNTHESIZED_WIRE_30;
+reg	DFF_00_inst17;
+reg	DFF_00_inst11;
+reg	DFF_00_inst12;
+reg	DFF_00_inst13;
+reg	DFF_00_inst14;
+reg	DFF_00_inst15;
+wire	SYNTHESIZED_WIRE_31;
+reg	DFF_00_inst2;
+reg	DFF_00_inst1;
+wire	[31:0] SYNTHESIZED_WIRE_21;
+wire	[31:0] SYNTHESIZED_WIRE_22;
+wire	[31:0] SYNTHESIZED_WIRE_23;
+wire	[31:0] SYNTHESIZED_WIRE_24;
+wire	[31:0] SYNTHESIZED_WIRE_25;
+wire	[31:0] SYNTHESIZED_WIRE_26;
+wire	[31:0] SYNTHESIZED_WIRE_27;
+wire	[31:0] SYNTHESIZED_WIRE_28;
+
+assign	SYNTHESIZED_WIRE_29 = 1;
+assign	SYNTHESIZED_WIRE_30 = 1;
+assign	SYNTHESIZED_WIRE_31 = 1;
+
+
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_29)
+begin
+if (!SYNTHESIZED_WIRE_29)
+	begin
+	DFF_00_inst0 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_29)
+	begin
+	DFF_00_inst0 <= 1;
+	end
+else
+	begin
+	DFF_00_inst0 <= start;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_29)
+begin
+if (!SYNTHESIZED_WIRE_29)
+	begin
+	DFF_00_inst1 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_29)
+	begin
+	DFF_00_inst1 <= 1;
+	end
+else
+	begin
+	DFF_00_inst1 <= DFF_00_inst0;
+	end
+end
+
+
+cordic_t	b2v_00_inst10(
+	.clk(clk),
+	.clk_en(en),
+	.reset(reset),
+	.dataa(SYNTHESIZED_WIRE_4),
+	.result(SYNTHESIZED_WIRE_27));
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst11 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst11 <= 1;
+	end
+else
+	begin
+	DFF_00_inst11 <= DFF_00_inst17;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst12 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst12 <= 1;
+	end
+else
+	begin
+	DFF_00_inst12 <= DFF_00_inst11;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst13 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst13 <= 1;
+	end
+else
+	begin
+	DFF_00_inst13 <= DFF_00_inst12;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst14 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst14 <= 1;
+	end
+else
+	begin
+	DFF_00_inst14 <= DFF_00_inst13;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst15 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	DFF_00_inst15 <= 1;
+	end
+else
+	begin
+	DFF_00_inst15 <= DFF_00_inst14;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_30 or negedge SYNTHESIZED_WIRE_30)
+begin
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	done <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_30)
+	begin
+	done <= 1;
+	end
+else
+	begin
+	done <= DFF_00_inst15;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_31 or negedge SYNTHESIZED_WIRE_31)
+begin
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst17 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_31)
+	begin
+	DFF_00_inst17 <= 1;
+	end
+else
+	begin
+	DFF_00_inst17 <= DFF_00_inst2;
+	end
+end
+
+
+always@(posedge clk or negedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_29)
+begin
+if (!SYNTHESIZED_WIRE_29)
+	begin
+	DFF_00_inst2 <= 0;
+	end
+else
+if (!SYNTHESIZED_WIRE_29)
+	begin
+	DFF_00_inst2 <= 1;
+	end
+else
+	begin
+	DFF_00_inst2 <= DFF_00_inst1;
+	end
+end
+
+
+fp_mul	b2v_00_inst4(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(dataa),
+	.b(dataa),
+	.q(SYNTHESIZED_WIRE_23));
+
+
+fp_div128	b2v_00_inst5(
+	.dataa(SYNTHESIZED_WIRE_21),
+	.result(SYNTHESIZED_WIRE_28));
+
+
+fp_div2	b2v_00_inst6(
+	.dataa(dataa),
+	.result(SYNTHESIZED_WIRE_26));
+
+
+fp_sub	b2v_00_inst7(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(dataa),
+	.b(SYNTHESIZED_WIRE_22),
+	.q(SYNTHESIZED_WIRE_21));
+
+
+fp_mul	b2v_00_inst8(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_23),
+	.b(SYNTHESIZED_WIRE_24),
+	.q(SYNTHESIZED_WIRE_25));
+
+
+fp_add	b2v_00_inst9(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_25),
+	.b(SYNTHESIZED_WIRE_26),
+	.q(result));
+
+
+fix_to_fp	b2v_inst(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_27),
+	.q(SYNTHESIZED_WIRE_24));
+
+
+fp_to_fix	b2v_inst1(
+	.clk(clk),
+	.areset(reset),
+	.en(en),
+	.a(SYNTHESIZED_WIRE_28),
+	.q(SYNTHESIZED_WIRE_4));
+
+
+
+const128	b2v_inst4(
+	.result(SYNTHESIZED_WIRE_22));
+
+
+
+
+endmodule
diff --git a/system_template_de1_soc/lpm_constant_0.v b/system_template_de1_soc/lpm_constant_0.v
new file mode 100644
index 0000000..6f38171
--- /dev/null
+++ b/system_template_de1_soc/lpm_constant_0.v
@@ -0,0 +1,28 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// PROGRAM		"Quartus Prime"
+// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+// CREATED		"Tue Mar 22 13:32:16 2022"
+
+
+module lpm_constant_0(result);
+output [31:0] result;
+
+lpm_constant	lpm_instance(.result(result));
+	defparam	lpm_instance.LPM_CVALUE = 32'b01000011000000000000000000000000;
+	defparam	lpm_instance.LPM_WIDTH = 32;
+
+endmodule
diff --git a/system_template_de1_soc/lpm_constant_1.v b/system_template_de1_soc/lpm_constant_1.v
new file mode 100644
index 0000000..5a155e3
--- /dev/null
+++ b/system_template_de1_soc/lpm_constant_1.v
@@ -0,0 +1,28 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// PROGRAM		"Quartus Prime"
+// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+// CREATED		"Tue Mar 22 12:03:47 2022"
+
+
+module lpm_constant_1(result);
+output [31:0] result;
+
+lpm_constant	lpm_instance(.result(result));
+	defparam	lpm_instance.LPM_CVALUE = 32'b00000000000000000000000000000000;
+	defparam	lpm_instance.LPM_WIDTH = 32;
+
+endmodule
diff --git a/system_template_de1_soc/pll.v b/system_template_de1_soc/pll.v
index 960e21a..d9b4627 100644
--- a/system_template_de1_soc/pll.v
+++ b/system_template_de1_soc/pll.v
@@ -1,8 +1,8 @@
-// megafunction wizard: %PLL Intel FPGA IP v20.1%
+// megafunction wizard: %PLL Intel FPGA IP v21.1%
 // GENERATION: XML
 // pll.v
 
-// Generated using ACDS version 20.1 711
+// Generated using ACDS version 21.1 842
 
 `timescale 1 ps / 1 ps
 module pll (
@@ -47,12 +47,12 @@ endmodule
 //	their respective licensors.  No other licenses, including any licenses
 //	needed under any third party's intellectual property, are provided herein.
 //-->
-// Retrieval info: <instance entity-name="altera_pll" version="20.1" >
+// Retrieval info: <instance entity-name="altera_pll" version="21.1" >
 // Retrieval info: 	<generic name="debug_print_output" value="false" />
 // Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
 // Retrieval info: 	<generic name="device_family" value="Cyclone V" />
-// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
-// Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />
+// Retrieval info: 	<generic name="device" value="Unknown" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
 // Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
 // Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
 // Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />