ELEC60011-DSD-CW/.gitignore

**
!system_template_de1_soc/
!*.bdf
!*.sdc
!*.v
!*.vhd
!*.sopcinfo
!*.tcl
!*.qip
!*.qpf
!*.qsf
!*.qsys
!system_template_de1_soc/software/
!system_template_de1_soc/software/**
system_template_de1_soc/software/*_bsp
!system_template_de1_soc/software/*/*.c
!DSD_coursework_DE1-SoC.pdf
!Report_3_Group_7.pdf
!README.md
!Python/
!*.py
Initial Commit Include Coursework PDF and basic test script for checking answer in Python 2022-01-25 16:48:03 +00:00			`**`
Add specific entries to .gitignore For Verilog and C source files within project 2022-01-30 17:17:51 +00:00			`!system_template_de1_soc/`
Add remaining project files and final report 2022-09-16 11:11:39 +00:00			`!*.bdf`
			`!*.sdc`
Initial Commit Include Coursework PDF and basic test script for checking answer in Python 2022-01-25 16:48:03 +00:00			`!*.v`
Add remaining project files and final report 2022-09-16 11:11:39 +00:00			`!*.vhd`
			`!*.sopcinfo`
			`!*.tcl`
			`!*.qip`
			`!*.qpf`
			`!*.qsf`
Initial Commit Include Coursework PDF and basic test script for checking answer in Python 2022-01-25 16:48:03 +00:00			`!*.qsys`
Add specific entries to .gitignore For Verilog and C source files within project 2022-01-30 17:17:51 +00:00			`!system_template_de1_soc/software/`
Add remaining project files and final report 2022-09-16 11:11:39 +00:00			`!system_template_de1_soc/software/**`
Add specific entries to .gitignore For Verilog and C source files within project 2022-01-30 17:17:51 +00:00			`system_template_de1_soc/software/*_bsp`
			`!system_template_de1_soc/software//.c`
Initial Commit Include Coursework PDF and basic test script for checking answer in Python 2022-01-25 16:48:03 +00:00			`!DSD_coursework_DE1-SoC.pdf`
Add remaining project files and final report 2022-09-16 11:11:39 +00:00			`!Report_3_Group_7.pdf`
Initial Commit Include Coursework PDF and basic test script for checking answer in Python 2022-01-25 16:48:03 +00:00			`!README.md`
			`!Python/`
			`!*.py`